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81. 发明申请

US20030113985A1 FIELD EFFECT TRANSISTOR SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：场效应晶体管半导体及其制造方法
公开(公告)号：US20030113985A1
公开(公告)日：2003-06-19
申请号：US09391507
申请日：1999-09-08
发明人： SHIGEYUKI MURAI , EMI FUJII , SHIGEHARU MATSUSHITA , HISAAKI TOMINAGA
IPC分类号： H01L021/338 , H01L021/8238 , H01L023/48 , H01L029/80
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/42316 , H01L29/812
摘要： This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11. The gate electrode 11 covers a part of the insulating film 7 and the surface of the GaAs substrate serving as the channel region, and a bottom metallic layer 8 contained in the gate electrode 11 is covered with a second metallic layer 9 which is highly adhesive to the insulating film 7.
摘要翻译：本发明的目的是提供一种场效应晶体管半导体，其在栅极金属和限定栅电极端的绝缘膜之间具有很大的粘附性并提高其产率。本发明的场效晶体管半导体包括位于GaAs衬底1中的预定位置的源极/漏电极6，设置在GaAs衬底1中以及在源极/漏极6之间的沟道区，栅电极11 与沟道区域的一部分肖特基接触并且位于源极/漏极6之间，并且在栅电极11的两个侧表面与GaAs衬底的表面和栅电极11电绝缘的绝缘膜7。栅电极11覆盖绝缘膜7的一部分和用作沟道区的GaAs衬底的表面，并且包含在栅电极11中的底部金属层8被第二金属层9覆盖，第二金属层9与绝缘膜7。

82. 发明授权

US06521961B1 Semiconductor device using a barrier layer between the gate electrode and substrate and method therefor 有权
标题翻译：在栅电极和衬底之间使用阻挡层的半导体器件及其方法
公开(公告)号：US06521961B1
公开(公告)日：2003-02-18
申请号：US09560737
申请日：2000-04-28
申请人： Julio Costa , Ernest Schirmann , Nyles W. Cody , Marino J. Martinez
发明人： Julio Costa , Ernest Schirmann , Nyles W. Cody , Marino J. Martinez
IPC分类号： H01L3106
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/475 , H01L29/66462
摘要： An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.
摘要翻译：增强型半导体器件具有设置在器件的栅极电极和栅极电极下方的半导体衬底之间的势垒层。阻挡层增加了栅电极 - 阻挡层 - 衬底界面的肖特基势垒高度，使得栅电极下面的衬底的部分以增强模式工作。阻挡层是特别有用的化合物半导体场效应晶体管，并且阻挡层的优选材料包括砷化铝镓和砷化铟镓。

83. 发明申请

US20030017660A1 GaAs MESFET having LDD and non-uniform P-well doping profiles 审中-公开
公开(公告)号：US20030017660A1
公开(公告)日：2003-01-23
申请号：US10237596
申请日：2002-09-10
申请人： Anadigics, Inc.
发明人： Weiqi Li
IPC分类号： H01L021/338 , H01L021/425
CPC分类号： H01L29/66871 , H01L29/1029 , H01L29/8128
摘要： A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type region is provided beneath the first portion, but not necessarily behind the second portion.

84. 发明申请

US20020195618A1 Semiconductor device and manufacturing method of the same 审中-公开
公开(公告)号：US20020195618A1
公开(公告)日：2002-12-26
申请号：US10216835
申请日：2002-08-13
申请人： Fujitsu Limited
发明人： Mizuhisa Nihei , Yuu Watanabe
IPC分类号： H01L021/338
CPC分类号： H01L29/66871 , H01L21/28575 , H01L29/42316
摘要： A gate electrode rectangular in section is formed by patterning on a GaAs substrate as a compound substrate having a channel layer. Subsequently, a specific metal, e.g., Ti is deposited. A solid-phase reaction layer to serve as source/drain is formed in a self-alignment manner with the gate electrode by a thermal treatment. The part of the Ti film which has not been reacted is then removed. Thus the source/drain (or at least one of them) are very easily formed to a shallow junction depth without using any ion implantation process. Realized is a semiconductor device showing an excellent device characteristics, capable of suppressing occurrence of short-channel effect even in its shortened gate length for reducing the device size.

85. 发明授权

US06383853B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06383853B2
公开(公告)日：2002-05-07
申请号：US09799049
申请日：2001-03-06
申请人： Shinichi Hoshi
发明人： Shinichi Hoshi
IPC分类号： H01L21338
CPC分类号： H01L29/66871 , H01L21/0331 , H01L21/0337 , H01L21/0338 , H01L21/28581 , H01L21/28587
摘要： A method of fabricating a semiconductor device, capable of forming a pattern more finely and more variously without depending on the performance of an exposing device. Aluminum is vapor deposited on a spacer film from an oblique direction to form a metal film etching guard. Specifically, Al is vapor deposited from a direction inclined from the direction of the normal line of the surface of the spacer film by 85° (angle of vapor deposition). For example, when the depth of a recess is 0.10 &mgr;m and the opening width is 0.4 &mgr;m, Al is not vapor deposited on the bottom surface of the recess. After performing anisotropic etching on the spacer film by using the metal film etching guard as a mask, the metal film etching guard is removed. A gate electrode is formed in the recess.
摘要翻译：一种制造半导体器件的方法，能够在不依赖于曝光器件的性能的情况下更精细地形成图案。从倾斜方向将铝蒸镀在间隔膜上，形成金属膜蚀刻保护层。具体而言，从间隔膜表面的法线方向倾斜85°（气相沉积角）的方向蒸镀Al。例如，当凹槽的深度为0.10μm，开口宽度为0.4μm时，Al不会在凹部的底表面上气相沉积。通过使用金属膜蚀刻保护膜作为掩模对间隔膜进行各向异性蚀刻后，去除金属膜蚀刻保护层。在凹部中形成栅电极。

86. 发明授权

US06355951B1 Field effect semiconductor device 失效
标题翻译：场效半导体器件
公开(公告)号：US06355951B1
公开(公告)日：2002-03-12
申请号：US09445957
申请日：1999-12-16
申请人： Ryo Hattori
发明人： Ryo Hattori
IPC分类号： H01L3300
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/1075 , H01L29/155 , H01L29/66462
摘要： In a field effect transistor such as high output FET or low noise HEMT, a layer for facilitating re-combination of carriers (for example a superlattice buffer layer), an undoped compound semiconductor layer having a higher resistance than a channel layer and the channel layer made of a compound semiconductor are layered successively. In the layer for facilitating re-combination of carriers, for example, oxygen of high concentration is introduced, to facilitate the non-radiative recombination which shortens the life of injected carriers. The layer for facilitating re-combination of carriers is also formed by forming the superlattice layer at a lower temperature than the channel layer. Thus, efficiency and voltageproofness on high frequency, high output power operation is improved further, and noises can be decreased further on high frequency, low noise operation.
摘要翻译：在诸如高输出FET或低噪声HEMT的场效应晶体管中，用于促进载流子（例如超晶格缓冲层）的重新组合的层，具有比沟道层更高的电阻的未掺杂化合物半导体层和沟道层由化合物半导体构成。在促进载体再结合的层中，例如，引入高浓度的氧，以促进非辐射复合，这缩短了注入载体的寿命。用于促进载流子再组合的层也通过在比沟道层低的温度下形成超晶格层来形成。因此，高频率，高输出功率运行的效率和电压进一步提高，在高频，低噪声运行时噪声可进一步降低。

87. 发明授权

US06255679B1 Field effect transistor which can operate stably in millimeter wave band 失效
标题翻译：场效应晶体管可在毫米波段内稳定工作
公开(公告)号：US06255679B1
公开(公告)日：2001-07-03
申请号：US09332223
申请日：1999-06-14
申请人： Yasuhiro Akiba
发明人： Yasuhiro Akiba
IPC分类号： H01L29812
CPC分类号： H01L29/66871 , H01L29/8128
摘要： In order to achieve an aspect of the present invention, in a field effect transistor, a compound semiconductor substrate has an active region, and a gate finger electrode is formed on the active region. Source and drain stripe electrodes are formed on the active region to sandwich the gate finger electrode apart from the gate finger electrode. An extended gate electrode is connected with the gate finger electrode and extended source and drain electrodes are connected with the source and drain stripe electrodes, respectively. A resistance section is provided between the gate finger electrode and the extended gate electrode in the transistor forming region.
摘要翻译：为了实现本发明的一个方面，在场效应晶体管中，化合物半导体衬底具有有源区，并且在有源区上形成栅指电极。源极和漏极条形电极形成在有源区上以将栅极指状电极夹在栅极指状电极之外。扩展栅电极与栅极指状电极连接，扩展源极和漏极分别与源极和漏极条电极连接。在晶体管形成区域中的栅极指状电极和延伸的栅电极之间设置有电阻部。

88. 发明授权

US06171912B2 Method of manufacturing a semiconductor device comprising a field effect transistor 有权
公开(公告)号：US06171912B2
公开(公告)日：2001-01-09
申请号：US09196067
申请日：1998-11-19
申请人： Louis Praamsma
发明人： Louis Praamsma
IPC分类号： H01L21336
CPC分类号： H01L29/7835 , H01L21/28114 , H01L21/2815 , H01L29/1045 , H01L29/402 , H01L29/42316 , H01L29/42376 , H01L29/4925 , H01L29/66659 , H01L29/66871
摘要： The invention relates to a method of manufacturing a field effect transistor, in particular a discrete field effect transistor, comprising a source region (1) and a drain region (2) and, between said regions, a channel region (4) above which a gate region (3) is located. The gate region (3) is formed by applying an insulating layer (5) to the semiconductor body and providing this insulating layer with a stepped portion (6) in the thickness direction, whereafter a conductive layer (30) is applied to the surface of the semiconductor body (10), which layer is substantially removed again by etching, so that a part (3A) of the conductive layer (30), which part forms part of the gate region (3) and which lies against the stepped portion (6), remains intact. In a method in accordance with the invention, the source region (1) and the drain region (2) are formed before the insulating layer (5) is provided, and after the provision of the part (3A) of the gate region (3), which part is formed from the conductive layer (30), the surface of the semiconductor body (10) is made flat by applying a further insulating layer (7) next to the stepped portion (6). Such a method enables a T-shaped gate region (3) to be manufactured in a simple manner, said gate region comprising a very short vertical part (3A) of, for example, polycrystalline silicon and an overlying wider horizontal part of, for example, aluminium. Such a transistor has excellent high-frequency properties. In a preferred embodiment, the stepped portion (6) is formed by providing the insulating layer with a recess (8) whose side walls are situated above the source region (1) and the channel region (4). In a particularly simple variant, a “parasitic” gate region (32) is subsequently formed above the source region (1), which is not objectionable. The recess (8) can further be used in the formation of LDMOST whose source region (1) can be provided with an extension (1A).

89. 发明授权

US5982023A Semiconductor device and field effect transistor 失效
标题翻译：半导体器件和场效应晶体管
公开(公告)号：US5982023A
公开(公告)日：1999-11-09
申请号：US951160
申请日：1997-10-15
申请人： Shigeharu Matsushita , Emi Fujii , Daijiro Inoue
发明人： Shigeharu Matsushita , Emi Fujii , Daijiro Inoue
IPC分类号： H01L21/285 , H01L21/338 , H01L21/76 , H01L29/812 , H01L29/06 , H01L29/80 , H01L31/0328
CPC分类号： H01L29/66871 , H01L21/28587 , H01L21/7605 , H01L29/812
摘要： A dummy gate is removed together with an SiO.sub.2 film thereon by lift-off to form a reverse dummy-gate pattern with the SiO.sub.2 film. A photoresist pattern is formed to cover the reverse dummy-gate pattern and an SiN protection film therebetween, and a mesa pattern is formed by mesa etching. The photoresist pattern is etched so that the edge of the photoresist pattern is located between the edge of the mesa pattern and the edge of the reverse dummy-gate pattern and the exposed part of the SiN protection film is etched. The edge of the SiN protection film is thus located inside the edge of the mesa pattern.
摘要翻译：通过剥离将虚拟栅极与其上的SiO 2膜一起除去，以形成具有SiO 2膜的反虚拟栅极图案。形成光致抗蚀剂图案以覆盖其间的反虚拟栅极图案和SiN保护膜，并且通过台面蚀刻形成台面图案。蚀刻光致抗蚀剂图案，使得光致抗蚀剂图案的边缘位于台面图案的边缘和反虚拟栅极图案的边缘之间，并且SiN保护膜的暴露部分被蚀刻。因此，SiN保护膜的边缘位于台面图案的边缘内。

90. 发明授权

US5869364A Single layer integrated metal process for metal semiconductor field effect transistor (MESFET) 失效
标题翻译：金属半导体场效应晶体管（MESFET）的单层集成金属工艺
公开(公告)号：US5869364A
公开(公告)日：1999-02-09
申请号：US684760
申请日：1996-07-22
申请人： Kenichi Nakano , Christopher A. Bozada , Tony K. Quach , Gregory C. DeSalvo , G. David Via , Ross W. Dettmer , Charles K. Havasy , James S. Sewell , John L. Ebel , James K. Gillespie
发明人： Kenichi Nakano , Christopher A. Bozada , Tony K. Quach , Gregory C. DeSalvo , G. David Via , Ross W. Dettmer , Charles K. Havasy , James S. Sewell , John L. Ebel , James K. Gillespie
IPC分类号： H01L21/338
CPC分类号： H01L29/812 , H01L21/28581 , H01L29/452 , H01L29/475 , H01L29/66871
摘要： A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state-of-the-art electrical performance.
摘要翻译：描述了周期表III-IV族金属半导体金属场效应晶体管器件的制造方法。所公开的制造装置对欧姆和肖特基势垒接触使用单一金属化，采用永久蚀刻停止层的选择性蚀刻，采用非合金欧姆接触半导体层并且包括永久非光敏次级掩模元件。本发明包括用于全光学光刻工艺和组合的光学和电子束光刻工艺的设备。这些概念被组合以提供减小制造成本，增加的尺寸精度和最先进的电气性能的场效应晶体管器件。

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