专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US6163051A High breakdown voltage semiconductor device 失效
标题翻译：高击穿电压半导体器件
公开(公告)号：US6163051A
公开(公告)日：2000-12-19
申请号：US154041
申请日：1998-09-16
申请人： Akio Nakagawa , Tomoko Matsudai , Hideyuki Funaki , Norio Yasuhara
发明人： Akio Nakagawa , Tomoko Matsudai , Hideyuki Funaki , Norio Yasuhara
IPC分类号： H01L21/331 , H01L29/06 , H01L29/739 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66325 , H01L29/0696 , H01L29/7394 , H01L29/7398
摘要： A high breakdown voltage semiconductor device comprising a first base region of a first conductivity type, a second base region of a second conductivity type, which is formed in a surface region of the first base region, a first gate insulation film formed on an inner wall of a first LOCOS groove formed passing through the second base region to reach the first base region, a first gate electrode formed on the first gate insulation film, a first source region of a first conductivity type, which is formed in a surface region of the second base region around the first LOCOS groove in such a manner as to contact with the first gate insulating film, a first drain region formed in a surface region of the first base region in such a manner as to be spaced apart from the second base region, a source electrode formed on the first source region and on the second base region, and a drain electrode formed on the first drain region.
摘要翻译：一种高耐压电压半导体器件，包括第一导电类型的第一基极区域和形成在第一基极区域的表面区域中的第二导电类型的第二基极区域，形成在内壁上的第一栅极绝缘膜形成为穿过第二基极区域以到达第一基极区域的第一LOCOS沟槽，形成在第一栅极绝缘膜上的第一栅极电极，形成在第一栅极绝缘膜的表面区域中的第一导电类型的第一源极区域，第二基区，以与第一栅极绝缘膜接触的方式围绕第一LOCOS沟槽;第一漏极区，形成在第一基极区域的表面区域中，以与第二基极区域隔开; 形成在第一源极区域和第二基极区域上的源电极以及形成在第一漏极区域上的漏电极。

82. 发明授权

US6117734A Method of forming a trench MOS gate on a power semiconductor device 失效
标题翻译：在功率半导体器件上形成沟槽MOS栅极的方法
公开(公告)号：US6117734A
公开(公告)日：2000-09-12
申请号：US996041
申请日：1997-12-22
申请人： Katsumi Nakamura
发明人： Katsumi Nakamura
IPC分类号： H01L29/74 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/06 , H01L29/24 , H01L29/423 , H01L29/739 , H01L29/749 , H01L29/78 , H01L29/786 , H01L29/861 , H01L21/3205
CPC分类号： H01L29/7824 , H01L21/76232 , H01L21/76264 , H01L21/763 , H01L29/0696 , H01L29/4236 , H01L29/66325 , H01L29/66348 , H01L29/66356 , H01L29/66378 , H01L29/66666 , H01L29/7391 , H01L29/7394 , H01L29/7397 , H01L29/7455 , H01L29/78 , H01L29/7801 , H01L29/7813 , H01L29/7827 , H01L21/76286 , H01L29/1608 , H01L29/42368
摘要： A method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.
摘要翻译：一种制造半导体器件的方法，其包括以下步骤：形成沟槽（4），并重复氧化膜（牺牲氧化物膜）的形成和去除两次以提供开口部分的圆形构型（5b）沟槽（4）和其底部的圆形构造（6b），并且将半导体层中的缺陷引入氧化硅膜（8）中，减少邻近沟槽（4）的内壁的缺陷，由此电场浓度阻止了栅极，并且为了功率器件的特性，特别是导通状态电压的改善，沟道中的载流子的迁移率得到改善。

83. 发明授权

US6075272A Structure for gated lateral bipolar transistors 失效
标题翻译：门控双极晶体管的结构
公开(公告)号：US6075272A
公开(公告)日：2000-06-13
申请号：US50266
申请日：1998-03-30
申请人： Leonard Forbes , Wendell P. Noble
发明人： Leonard Forbes , Wendell P. Noble
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/07 , H01L29/73 , H01L29/739 , H01L29/76 , H01L27/082
CPC分类号： H01L29/66325 , H01L21/8249 , H01L27/0705 , H01L29/7317 , H01L29/739 , H01L29/7394
摘要： An improved structure and method for gated lateral bipolar transistors is provided. The present invention capitalizes on opposing sidewall structures and adjacent conductive sidewall members to conserve available surface space on the semiconductor chips. The conserved surface space allows a higher density of structures per chip. The conductive sidewall members couple to the gate of the gated lateral bipolar transistor and, additionally, to a retrograded, more highly doped bottom layer. The improved structure provides for both metal-oxide semiconductor (MOS) type conduction and bipolar junction transistor (BJT) type conduction beneath the gate of the gated lateral bipolar transistor.
摘要翻译：提供了一种改进的门控双向晶体管的结构和方法。本发明利用相对的侧壁结构和相邻的导电侧壁构件来节省半导体芯片上的可用表面空间。保守的表面空间允许每芯片具有更高的结构密度。导电侧壁构件耦合到门控侧向双极晶体管的栅极，并且另外耦合到退化的，更高掺杂的底层。改进的结构提供在门控侧向双极晶体管的栅极下方的金属氧化物半导体（MOS）型导电和双极结型晶体管（BJT）型导电。

84. 发明授权

US5869850A Lateral insulated gate bipolar transistor 失效
标题翻译：横向绝缘栅双极晶体管
公开(公告)号：US5869850A
公开(公告)日：1999-02-09
申请号：US990077
申请日：1997-12-12
申请人： Koichi Endo , Nobuyuki Sato
发明人： Koichi Endo , Nobuyuki Sato
IPC分类号： H01L21/331 , H01L29/06 , H01L29/739 , H01L29/74
CPC分类号： H01L29/66325 , H01L29/0696 , H01L29/7393 , H01L29/7394
摘要： A lateral insulated gate bipolar transistor has an emitter region that is displaced from a main path for passing carriers from a collector region to a base region through a first semiconductor layer. This arrangement suppresses the operation of a parasitic transistor composed of the emitter region, base region, and first semiconductor layer and prevents a latch-up. The width of the gate electrode of covering the first semiconductor layer serving as a drift region of carriers may be widened to form a carrier accumulation layer in the first semiconductor layer adjacent to the gate electrode. The accumulation layer increases the total number of carriers in the drift region, to reduce a saturation voltage between the collector region and the emitter region. As a result, the lateral insulated gate bipolar transistor operates with a low voltage to reduce power consumption.
摘要翻译：横向绝缘栅双极晶体管具有从主路径偏移的发射极区域，用于使载流子从集电极区域通过第一半导体层通过基极区域。这种布置抑制由发射极区域，基极区域和第一半导体层构成的寄生晶体管的操作，并且防止闩锁。覆盖用作载流子漂移区域的第一半导体层的栅电极的宽度可以加宽，以在与栅电极相邻的第一半导体层中形成载流子堆积层。累积层增加了漂移区域中的载流子总数，以减小集电极区域和发射极区域之间的饱和电压。结果，横向绝缘栅双极晶体管以低电压工作以降低功耗。

85. 发明授权

US5572055A Insulated-gate bipolar transistor with reduced latch-up 失效
标题翻译：绝缘栅双极晶体管，具有减少的闭锁
公开(公告)号：US5572055A
公开(公告)日：1996-11-05
申请号：US491517
申请日：1995-06-19
申请人： Hitoshi Sumida
发明人： Hitoshi Sumida
IPC分类号： H01L21/331 , H01L29/06 , H01L29/739 , H01L29/76 , H01L29/74 , H01L29/94
CPC分类号： H01L29/0696 , H01L29/66325 , H01L29/7393 , H01L29/7398
摘要： An insulated-gate bipolar transistor includes a semiconductor region of a first conductive type; a base layer of a second conductive type diffused from a surface of the semiconductor region; a source layer of the first conductive type diffused in a surface portion of the base layer; an insulated gate buried in a recess dug from the surface of the source layer through the base layer up to the semiconductor region; a collector layer of the second conductive type diffused from a surface of the semiconductor region on an opposite side of the insulated gate with respect to the source layer; an emitter terminal drawn from the base layer and the source layer; a collector terminal drawn from the collector layer; and a gate terminal drawn from the insulated gate.
摘要翻译：绝缘栅双极晶体管包括第一导电类型的半导体区域; 从所述半导体区域的表面扩散的第二导电类型的基底层; 所述第一导电类型的源极层扩散在所述基底层的表面部分中; 埋置在从源极层的表面穿过基底层直到半导体区域的凹部中的绝缘栅极; 所述第二导电类型的集电极层相对于所述源极层从所述绝缘栅极的相对侧上的所述半导体区域的表面扩散; 从基层和源层绘制的发射极端子; 从集电极层抽出的集电极端子; 以及从绝缘栅极拉出的栅极端子。

86. 发明公开

US20240250158A1 LATERAL BIPOLAR TRANSISTORS WITH GATE STRUCTURE ALIGNED TO EXTRINSIC BASE 审中-公开
公开(公告)号：US20240250158A1
公开(公告)日：2024-07-25
申请号：US18438882
申请日：2024-02-12
申请人： GLOBALFOUNDRIES U.S. Inc.
发明人： Judson R. Holt , Vibhor Jain , Alexander M. Derrickson
IPC分类号： H01L29/739 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7393 , H01L29/0649 , H01L29/66325
摘要： The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

87. 发明授权

US12009413B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US12009413B2
公开(公告)日：2024-06-11
申请号：US17457320
申请日：2021-12-02
申请人： Mitsubishi Electric Corporation
发明人： Katsumi Nakamura
IPC分类号： H01L29/739 , H01L29/66
CPC分类号： H01L29/7397 , H01L29/66325
摘要： A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer.

88. 发明授权

US10868156B2 Method of forming epitaxial silicon layer and semiconductor device thereof 有权
公开(公告)号：US10868156B2
公开(公告)日：2020-12-15
申请号：US16726672
申请日：2019-12-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yu-Hung Cheng , Po-Jung Chiang , Yen-Hsiu Chen , Yeur-Luen Tu
IPC分类号： H01L21/00 , H01L29/739 , H01L29/66 , H01L21/02 , H01L21/768 , H01L21/3065 , H01L21/285 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/732
CPC分类号： H01L29/739 , H01L21/0245 , H01L21/0262 , H01L21/02532 , H01L21/02609 , H01L21/02636 , H01L21/02639 , H01L21/28518 , H01L21/3065 , H01L21/76895 , H01L29/0649 , H01L29/0813 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/66325 , H01L29/732 , H01L29/7325
摘要： A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, wherein a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer having a first sidewall adjacent to the gate structures and a first central portion; and, in the chamber, shaping the epitaxial silicon-rich layer to form a second sidewall adjacent to the gate structures and a second central portion, wherein a first height difference between the first sidewall and the first central portion is greater than a second height difference between the second sidewall and the second central portion.

89. 发明申请

US20180226398A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180226398A1
公开(公告)日：2018-08-09
申请号：US15694963
申请日：2017-09-04
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tsuneo OGURA , Tomoko MATSUDAI
IPC分类号： H01L27/06 , H01L29/739 , H01L29/868 , H01L29/10 , H01L29/40
CPC分类号： H01L27/0664 , H01L21/762 , H01L27/0635 , H01L27/0761 , H01L29/0615 , H01L29/1095 , H01L29/407 , H01L29/66325 , H01L29/739 , H01L29/7397 , H01L29/868
摘要： A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor region between the first semiconductor region and the second electrode, a third semiconductor region between the first semiconductor region and the second electrode, a fourth semiconductor region between the first semiconductor region and the first electrode, a third electrode between the first electrode and the first semiconductor region, a first insulating film between the third electrode and both the first electrode and the first semiconductor region, a fifth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, a sixth semiconductor region between the fourth semiconductor region and the first electrode and in contact with the first electrode, and a seventh semiconductor region between the fourth semiconductor region and the first insulating film and in contact with the first semiconductor region.

90. 发明申请

US20180053663A1 SEMICONDUCTOR COMPONENT, METHOD FOR PROCESSING A SUBSTRATE AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT 审中-公开
公开(公告)号：US20180053663A1
公开(公告)日：2018-02-22
申请号：US15677091
申请日：2017-08-15
申请人： Infineon Technologies AG
发明人： Mathias Plappert , Stefan Krivec , Andreas Riegler , Karin Schrettlinger
IPC分类号： H01L21/3215 , H01L23/29 , H01L29/739 , H01L29/66 , H01L29/06 , H01L23/31
CPC分类号： H01L21/32155 , H01L21/76886 , H01L23/293 , H01L23/298 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L29/0619 , H01L29/401 , H01L29/417 , H01L29/41716 , H01L29/66325 , H01L29/7393 , H01L29/7436
摘要： In various embodiments, a method is provided. The method includes forming a metallization layer above at least one first region of a substrate. After forming the metallization layer at least one second region of the substrate is free of the metallization layer. The method further includes forming a barrier layer above the at least one first region of the substrate and above the at least one second region of the substrate. The barrier layer in the at least one first region of the substrate directly adjoins the metallization layer. The method further includes removing the barrier layer in the at least one first region of the substrate by drive-in of the barrier layer into the metallization layer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式