专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US09595609B2 Semiconductor device including superjunction structure formed using angled implant process 有权
标题翻译：半导体器件包括使用成角度的注入工艺形成的超结构结构
公开(公告)号：US09595609B2
公开(公告)日：2017-03-14
申请号：US14860396
申请日：2015-09-21
申请人： Alpha and Omega Semiconductor Incorporated
发明人： Karthik Padmanabhan , Madhur Bobde , Lingpeng Guan , Lei Zhang , Hamza Yilmaz
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/265
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/324 , H01L29/0634 , H01L29/0653 , H01L29/0661 , H01L29/0676 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/42376 , H01L29/66689 , H01L29/7802 , H01L29/7803 , H01L29/7816 , H01L29/7823
摘要： A semiconductor device includes a superjunction structure formed using simultaneous N and P angled implants into the sidewall of a trench. The simultaneous N and P angled implants use different implant energies and dopants of different diffusion rate so that after annealing, alternating N and P thin semiconductor regions are formed. The alternating N and P thin semiconductor regions form a superjunction structure where a balanced space charge region is formed to enhance the breakdown voltage characteristic of the semiconductor device.
摘要翻译：半导体器件包括使用同时进入沟槽侧壁中的N和P角植入物形成的超结结构。同时的N和P倾斜植入物使用不同的扩散速率的不同注入能量和掺杂剂，使得在退火之后，形成交替的N和P薄半导体区域。交替的N和P薄半导体区域形成超结构结构，其中形成平衡空间电荷区域以增强半导体器件的击穿电压特性。

82. 发明授权

US09595608B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09595608B2
公开(公告)日：2017-03-14
申请号：US14621369
申请日：2015-02-12
申请人： FUJI ELECTRIC CO., LTD.
发明人： Naoki Kumagai
IPC分类号： H01L29/78 , H01L29/06 , H01L21/04 , H01L29/66 , H01L29/10 , H01L29/08 , H01L29/739 , H01L29/16 , H01L29/20
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/0634 , H01L29/0684 , H01L29/0878 , H01L29/0886 , H01L29/1095 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/7395
摘要： An n− drift region is disposed on the front surface of an n+ semiconductor substrate composed of a wide band gap semiconductor. A p-channel region is selectively disposed on the surface layer of the n− drift region. A high-concentration p+ base region is disposed so as to adjoin the lower portion of the p-channel region inside the n− drift region. Inside the high-concentration p+ base region, an n+ high-concentration region is selectively disposed at the n+ semiconductor substrate side. The n+ high-concentration region has a stripe-shaped planar layout extending to the direction that the high-concentration p+ base regions line up. The n+ high-concentration region adjoins a JFET region at one end portion in longitudinal direction of the stripe. Further, the n+ semiconductor substrate side of the n+ high-concentration region adjoins the part sandwiched between the high-concentration p+ base region and the n+ semiconductor substrate in the n− drift region.
摘要翻译：在由宽带隙半导体构成的n +半导体衬底的前表面上设置n-漂移区。 p沟道区选择性地设置在n-漂移区的表面层上。高浓度p +基区域被配置成与n漂移区域内部的p沟道区域的下部相邻。在高浓度p +碱基区域内，在n +半导体衬底侧选择性地设置n +高浓度区域。 n +高浓度区域具有向高浓度p +碱基区域排列的方向延伸的条状平面布局。 n +高浓度区域在条带的纵向方向上的一个端部邻接JFET区域。此外，n +高浓度区域的n +半导体衬底侧与夹在n漂移区域中的高浓度p +基极区域和n +半导体衬底之间的部分相邻。

83. 发明授权

US09595596B2 Superjunction structures for power devices 有权
标题翻译：功率器件的超结构
公开(公告)号：US09595596B2
公开(公告)日：2017-03-14
申请号：US14589544
申请日：2015-01-05
申请人： Fairchild Semiconductor Corporation
发明人： Joseph A. Yedinak , Jaegil Lee , Chongman Yun , Praveen Muraleedharan Shenoy , Christopher L. Rexer
IPC分类号： H01L29/66 , H01L29/78 , H01L21/02 , H01L21/265 , H01L21/306 , H01L29/739 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40
CPC分类号： H01L29/66712 , H01L21/02532 , H01L21/26513 , H01L21/30604 , H01L29/0615 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1075 , H01L29/1095 , H01L29/404 , H01L29/7395 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one general aspect, a power device can include an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type. The power device can include a termination region surrounding at least a portion of the active region and can have a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type. Each of the plurality of pillars of the first conductivity type in the active region and the termination region can be defined by a trench. The power device can include an enrichment region at a bottom portion of one of the plurality of pillars of the first conductivity type in the active region.
摘要翻译：在一个一般方面，功率器件可以包括具有交替地布置有多个第二导电类型的柱的第一导电类型的多个柱的有源区。功率器件可以包括围绕有源区域的至少一部分的终端区域，并且可以具有多个第一导电类型的柱，其交替地布置有多个第二导电类型的柱。有源区域中的第一导电类型的多个支柱中的每一个和端接区域可以由沟槽限定。功率器件可以在有源区域中包括在第一导电类型的多个支柱之一的底部的富集区域。

84. 发明申请

US20170069751A1 VERTICAL POWER MOSFET 审中-公开
标题翻译：垂直功率MOSFET
公开(公告)号：US20170069751A1
公开(公告)日：2017-03-09
申请号：US15355583
申请日：2016-11-18
申请人： Renesas Electronics Corporation
发明人： Tomohiro TAMAKI
IPC分类号： H01L29/78 , H01L29/08 , H01L29/66 , H01L29/417 , H01L21/04 , H01L29/16 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7811 , H01L21/046 , H01L29/0634 , H01L29/0696 , H01L29/0865 , H01L29/0869 , H01L29/0878 , H01L29/0882 , H01L29/1095 , H01L29/1608 , H01L29/41741 , H01L29/4238 , H01L29/66068 , H01L29/66712 , H01L29/66727 , H01L29/66734 , H01L29/7802 , H01L29/7813
摘要： Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.
摘要翻译：具有超级结的垂直功率MOSFET是能够比其他垂直功率MOSFET具有更低导通电阻的器件。虽然它们具有由于切换操作中的关闭时N型漂移区的快速耗尽而具有高速切换的优点，但是它们可能引起振铃。本发明提供的具有超结结构的垂直功率MOSFET在栅电极下的第一导电类型漂移区的表面区域具有深度比第二导电类型深的浅底栅重掺杂N型区并且其浓度高于第一导电类型漂移区域的浓度。

85. 发明申请

US20170069727A1 POWER DEVICE HAVING A POLYSILICON-FILLED TRENCH WITH A TAPERED OXIDE THICKNESS 有权
标题翻译：具有氧化锌厚度的多晶硅填充的电源装置
公开(公告)号：US20170069727A1
公开(公告)日：2017-03-09
申请号：US15247510
申请日：2016-08-25
申请人： MaxPower Semiconductor, Inc.
发明人： Richard A. Blanchard , Mohamed N. Darwish , Jun Zeng
IPC分类号： H01L29/40 , H01L29/66 , H01L29/06 , H01L29/16 , H01L29/78 , H01L29/10
CPC分类号： H01L29/66068 , H01L21/047 , H01L21/26586 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/1037 , H01L29/1095 , H01L29/16 , H01L29/1608 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/66734 , H01L29/7813
摘要： In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.
摘要翻译：在一个实施例中，功率MOSFET垂直传导电流。底部电极可以连接到正电压，并且顶部电极可以连接到低电压，例如连接到地的负载。诸如多晶硅的栅极和/或场板在沟槽内。沟槽具有使多晶硅与硅壁绝缘的锥形氧化物层。在沟槽底部附近的氧化物比靠近顶部更厚，以增加击穿电压。通过将氮注入到沟槽壁中以形成锥形氮掺杂剂浓度来形成锥形氧化物。这在退火之后形成锥形氮化硅层。锥形氮化硅在随后的氧化步骤中可变地抑制氧化物生长。

86. 发明授权

US09590097B2 Semiconductor devices and related fabrication methods 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US09590097B2
公开(公告)日：2017-03-07
申请号：US15053745
申请日：2016-02-25
申请人： FREESCALE SEMICONDUCTOR INC.
发明人： Hongning Yang , Daniel J. Blomberg , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/06 , H01L29/10 , H01L29/08 , H01L21/265 , H01L29/40 , H01L29/66 , H01L29/786
CPC分类号： H01L29/7823 , H01L21/26513 , H01L29/0623 , H01L29/0634 , H01L29/0646 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/0886 , H01L29/1095 , H01L29/402 , H01L29/66689 , H01L29/7835 , H01L29/78624
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type. The first drift region resides laterally between the drain region and the junction isolation region, the junction isolation region resides laterally between the first drift region and the second drift region, and the second drift region resides laterally between the body region and the junction isolation region.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型的半导体材料的主体区域，在体区内具有第二导电类型的半导体材料的源极区域，具有第二导电类型的半导体材料的结隔离区域，漏极区域具有第二导电类型的半导体材料以及具有第二导电类型的半导体材料的第一和第二漂移区。第一漂移区域横向地位于漏极区域和结隔离区域之间，结隔离区域横向位于第一漂移区域和第二漂移区域之间，并且第二漂移区域横向居住在体区域和结隔离区域之间。

87. 发明授权

US09590093B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09590093B2
公开(公告)日：2017-03-07
申请号：US14642345
申请日：2015-03-09
申请人： Kabushiki Kaisha Toshiba
发明人： Syotaro Ono , Hideyuki Ura , Masahiro Shimura , Hiroaki Yamashita
IPC分类号： H01L29/73 , H01L29/78 , H01L29/739 , H01L29/10 , H01L29/08 , H01L29/36 , H01L29/06
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/086 , H01L29/0869 , H01L29/0878 , H01L29/0886 , H01L29/1095 , H01L29/36 , H01L29/66712 , H01L29/7395 , H01L29/7802
摘要： In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The third semiconductor region includes a first portion and a second portion. The first portion is provided between the second semiconductor regions adjacent to each other. An amount of impurity of the second conductivity type in the first portion is greater than an amount of impurity of the first conductivity type in the second semiconductor region contiguous to the first portion. The second portion is arranged with a part of the first semiconductor region. An amount of impurity of the second conductivity type in the second portion is smaller than an amount of impurity of the first conductivity type in the part of the first semiconductor region.
摘要翻译：通常，根据一个实施例，半导体器件包括第一半导体区域，多个第二半导体区域，多个第三半导体区域，第四半导体区域，第五半导体区域和栅电极。第三半导体区域包括第一部分和第二部分。第一部分设置在彼此相邻的第二半导体区域之间。第一部分中的第二导电类型的杂质的量大于与第一部分相邻的第二半导体区域中的第一导电类型的杂质的量。第二部分布置有第一半导体区域的一部分。第二部分中的第二导电类型的杂质的量小于第一半导体区域的部分中的第一导电类型的杂质的量。

88. 发明申请

US20170062611A1 REDUCED AREA POWER DEVICES USING DEEP TRENCH ISOLATION 审中-公开
标题翻译：减震区域使用深层隔离隔离装置
公开(公告)号：US20170062611A1
公开(公告)日：2017-03-02
申请号：US15348725
申请日：2016-11-10
申请人： Texas Instruments Incorporated
发明人： Yongxi ZHANG , Sameer PENDHARKAR , Seetharaman SRIDHAR
IPC分类号： H01L29/78 , H01L21/265 , H01L21/324 , H01L29/06 , H01L29/66 , H01L29/08 , H01L29/10 , H01L21/266 , H01L21/762
CPC分类号： H01L29/7823 , H01L21/26513 , H01L21/266 , H01L21/324 , H01L21/762 , H01L21/76224 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0865 , H01L29/0878 , H01L29/0882 , H01L29/1079 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： An integrated circuit including an isolated device which is isolated with a lower buried layer combined with deep trench isolation. An upper buried layer, with the same conductivity type as the substrate, is disposed over the lower buried layer, so that electrical contact to the lower buried layer is made at a perimeter of the isolated device. The deep trench isolation laterally surrounds the isolated device. Electrical contact to the lower buried layer sufficient to maintain a desired bias to the lower buried layer is made along less than half of the perimeter of the isolated device, between the upper buried layer and the deep trench.
摘要翻译：一种集成电路，包括隔离器件，隔离器件具有与深沟槽隔离相结合的较低埋层。具有与衬底相同的导电类型的上掩埋层设置在下掩埋层上，使得在隔离器件的周边处形成与下掩埋层的电接触。深沟槽隔离横向围绕隔离设备。在下埋层之间的电接触足以保持对下掩埋层的期望偏压，沿着隔离器件的周边的上半部分在上掩埋层和深沟槽之间进行。

89. 发明申请

US20170053987A1 TRANSISTOR STRUCTURES HAVING REDUCED ELECTRICAL FIELD AT THE GATE OXIDE AND METHODS FOR MAKING SAME 审中-公开
标题翻译：在栅极氧化物上具有减少电场的晶体管结构及其制造方法
公开(公告)号：US20170053987A1
公开(公告)日：2017-02-23
申请号：US15344735
申请日：2016-11-07
申请人： Cree, Inc.
发明人： Qingchun Zhang , Brett Hull
IPC分类号： H01L29/16 , H01L29/08 , H01L29/78 , H01L29/66 , H01L29/739 , H01L29/749 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0619 , H01L29/0623 , H01L29/0688 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66333 , H01L29/66378 , H01L29/66666 , H01L29/66712 , H01L29/7395 , H01L29/749 , H01L29/7827 , H01L29/7828
摘要： A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.
摘要翻译：公开了一种在栅极氧化物界面处具有减小的电场的晶体管器件。在一个实施例中，晶体管器件包括栅极，源极和漏极，其中栅极至少部分地与栅极氧化物接触。晶体管器件在晶体管器件的JFET区域内具有P +区域，以便减小栅极氧化物上的电场。

90. 发明授权

US09570566B2 Semiconductor device including a trench at least partially filled with a conductive material in a semiconductor substrate 有权
标题翻译：半导体器件包括在半导体衬底中至少部分地填充有导电材料的沟槽
公开(公告)号：US09570566B2
公开(公告)日：2017-02-14
申请号：US14879877
申请日：2015-10-09
申请人： Infineon Technologies Austria AG
发明人： Anton Mauder , Reinhard Ploss , Hans-Joachim Schulze
IPC分类号： H01L29/78 , H01L29/417 , H01L23/36 , H01L21/74 , H01L29/06 , H01L29/45 , H01L29/66 , H01L29/10 , H01L29/167 , H01L29/739 , H01L23/00 , H01L21/225 , H01L21/324 , H01L29/08
CPC分类号： H01L29/4236 , H01L21/2225 , H01L21/2251 , H01L21/2254 , H01L21/2255 , H01L21/2257 , H01L21/28079 , H01L21/30604 , H01L21/324 , H01L21/3247 , H01L21/743 , H01L23/36 , H01L24/05 , H01L29/0653 , H01L29/0657 , H01L29/0878 , H01L29/1079 , H01L29/167 , H01L29/41741 , H01L29/41766 , H01L29/456 , H01L29/4958 , H01L29/66333 , H01L29/66348 , H01L29/66666 , H01L29/66712 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7813 , H01L29/7827 , H01L2224/05009 , H01L2224/05078 , H01L2224/0557 , H01L2924/00014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first trench is at least partially filled with a conductive material and electrically connected to the semiconductor substrate via a doped semiconductor layer at a sidewall of the first trench. A semiconductor layer adjoins the semiconductor substrate at the first side, and caps the first trench at the first side. A contact is disposed at a second side of the semiconductor substrate opposite to the first side. A method of manufacturing the semiconductor device is also provided.
摘要翻译：半导体器件包括半导体衬底和从第一侧延伸到或穿过半导体衬底的第一沟槽。第一沟槽至少部分地填充有导电材料，并且通过第一沟槽的侧壁处的掺杂半导体层电连接到半导体衬底。半导体层在第一侧邻接半导体衬底，并且在第一侧覆盖第一沟槽。接触件设置在与第一侧相对的半导体衬底的第二侧。还提供了制造半导体器件的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式