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81. 发明申请

US20140134754A1 MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM 有权
标题翻译：用于防止减少电磁膜的半导体器件的制造方法
公开(公告)号：US20140134754A1
公开(公告)日：2014-05-15
申请号：US14157752
申请日：2014-01-17
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Katsuyoshi Matsuura
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01L27/11507 , H01L28/57
摘要： A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma.
摘要翻译：在半导体衬底上形成铁电电容器，所述强电介质电容器包括按所述顺序堆叠的下电极，铁电体膜和上电极。形成厚度等于或大于30nm的氧化铝的第一电容器保护膜，覆盖铁电电容器。通过使用高密度等离子体的化学气相沉积在第一电容器保护膜上形成氧化硅的第一绝缘膜。

82. 发明授权

US08709891B2 Method and system for utilizing Perovskite material for charge storage and as a dielectric 有权
标题翻译：利用钙钛矿材料进行电荷储存和电介质的方法和系统
公开(公告)号：US08709891B2
公开(公告)日：2014-04-29
申请号：US13918537
申请日：2013-06-14
申请人： Zhida Lan , Dongmin Chen
发明人： Zhida Lan , Dongmin Chen
IPC分类号： H01L21/8242
CPC分类号： G11C11/22 , G11C13/0007 , H01L21/28291 , H01L27/11507 , H01L28/55 , H01L29/51 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： Memory devices and methods for providing the memory devices are provided. The memory devices utilize multiple metal oxide layers. The methods for providing the memory devices can include providing a transistor; producing a capacitor that includes metal layers and metal oxide layers; connecting the capacitor to a side of the transistor; and providing a wordline, bitline, and driveline through connection with the transistor or the capacitor.
摘要翻译：提供了用于提供存储器件的存储器件和方法。存储器件利用多个金属氧化物层。用于提供存储器件的方法可以包括提供晶体管; 制造包括金属层和金属氧化物层的电容器; 将电容器连接到晶体管的一侧; 并通过与晶体管或电容器的连接来提供字线，位线和传动系。

83. 发明申请

US20140091429A1 MULTILAYER DIELECTRIC MEMORY DEVICE 有权
标题翻译：多层电介质存储器件
公开(公告)号：US20140091429A1
公开(公告)日：2014-04-03
申请号：US14039543
申请日：2013-09-27
申请人： Kyu S. Min
发明人： Kyu S. Min
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/75 , G11C13/0007 , G11C2213/54 , G11C2213/79 , H01L27/108 , H01L27/11507 , H01L28/40 , H01L28/56
摘要： A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship.
摘要翻译：存储器件具有多个介电阻挡区域。与具有单个屏障区域的存储器件相比，存储器件具有多个屏障区域，其提供更高或更低的电流 - 电压斜率。该器件还具有提供对电流 - 电压关系的进一步控制的电极区域。

84. 发明授权

US08674478B2 Semiconductor device having capacitor with upper electrode whose circumference is made long 有权
标题翻译：具有电容器的半导体器件具有长周长的上电极
公开(公告)号：US08674478B2
公开(公告)日：2014-03-18
申请号：US13212541
申请日：2011-08-18
申请人： Hirotoshi Tachibana
发明人： Hirotoshi Tachibana
IPC分类号： H01L29/92
CPC分类号： H01L28/55 , H01L27/11504 , H01L27/11507
摘要： A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 μm2 and L/S equal to or larger than 0.4 μm−1, where S is an area of a capacitor region in which the lower and upper electrodes face each other across the dielectric film, and L is a total length of a circumference line of the capacitor region.
摘要翻译：在半导体衬底上形成电容器。电容器包括下列电极，电容器电介质膜和上电极，其面积S等于或大于1000mum2，L / S等于或大于0.4mum-1，其中S为下电极和上电极在电介质膜上彼此面对的电容器区域的面积，L是电容器区域的周长线的总长度。

85. 发明授权

US08674473B2 Semiconductor cell and method for forming the same 有权
标题翻译：半导体电池及其形成方法
公开(公告)号：US08674473B2
公开(公告)日：2014-03-18
申请号：US13210909
申请日：2011-08-16
申请人： Song Hyeuk Im
发明人： Song Hyeuk Im
IPC分类号： H01L21/70
CPC分类号： H01L27/10855 , H01L21/764 , H01L21/7682 , H01L21/76831 , H01L21/76897 , H01L27/10885 , H01L27/11507
摘要： A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.
摘要翻译：半导体电池包括设置在半导体衬底上的存储节点接触插塞，位于存储节点接触插头之间并露出半导体衬底的位线形成区域，以及与侧壁的下侧接触的气隙位线形成区域并且在垂直于位线形成区域延伸的方向的方向上延伸。因此，控制相邻位线之间的耦合效应以及相邻存储节点接触插塞之间引起的耦合效应和存储节点接触插头与位线之间引起的耦合效应，以改善半导体器件的特性。

86. 发明申请

US20130313679A1 INTEGRATED CIRCUIT WITH INTEGRATED DECOUPLING CAPACITORS 审中-公开
标题翻译：集成电路与集成的去耦电容器
公开(公告)号：US20130313679A1
公开(公告)日：2013-11-28
申请号：US13953476
申请日：2013-07-29
申请人： Texas Instruments Incorporated
发明人： Scott Robert Summerfelt , John A. Rodriguez , Huang-Chun Wen , Steven Craig Bartling
IPC分类号： H01L27/08 , H01L27/06
CPC分类号： H01L27/0805 , H01L27/0207 , H01L27/06 , H01L27/11507 , H01L27/11509 , H01L28/55 , H01L29/92
摘要： Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.
摘要翻译：用于集成去耦电容器的铁电电容器结构等。铁电电容器结构包括在电压节点之间彼此串联连接的两个或更多个铁电电容器。铁电电容器的串联连接减少了施加的电压，使得能够使用由MOCVD沉积的诸如PZT的粗铁电介质材料。串联电容器的匹配结构以及每个电容器的施加电压的均匀极性有利于降低跨任何一个电容器的最大电压，从而降低了介质击穿的难度。

87. 发明授权

US08552515B2 Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps 有权
标题翻译：用于制造使用减少的处理步骤的镶嵌自对准铁电随机存取存储器（F-RAM）器件结构的方法
公开(公告)号：US08552515B2
公开(公告)日：2013-10-08
申请号：US13569735
申请日：2012-08-08
申请人： Shan Sun , Thomas E. Davenport , John Cronin
发明人： Shan Sun , Thomas E. Davenport , John Cronin
IPC分类号： H01L21/02
CPC分类号： H01L27/11507 , H01L28/55 , H01L28/75
摘要： Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.
摘要翻译：公开了一种新颖的非易失性铁电随机存取存储器（F-RAM）器件和一种使用减少数量的掩模和蚀刻步骤在平面上制造镶嵌自对准F-RAM器件结构的方法。

88. 发明授权

US08552484B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08552484B2
公开(公告)日：2013-10-08
申请号：US11647198
申请日：2006-12-29
申请人： Kouichi Nagai
发明人： Kouichi Nagai
IPC分类号： H01G7/06 , H01L27/108 , H01L29/76 , H01L29/92
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/65
摘要： The semiconductor device according to the present invention comprises: a ferroelectric capacitor 42 formed above a semiconductor substrate 10 and including a lower electrode 36, a ferroelectric film 38 formed on the lower electrode 36 and an upper electrode 40 formed on the ferroelectric film 38; a silicon oxide film 60 formed above the semiconductor substrate 10 and the ferroelectric capacitor 42 and having the surface planarized; a flat barrier film 62 formed on the silicon oxide film 60 with a silicon oxide film 61 formed therebetween, for preventing the diffusion of hydrogen or water; a silicon oxide film 64 formed above the barrier film 62 and having the surface planarized; and a flat barrier film 78 formed on the silicon oxide film 74 with a silicon oxide film 76 formed therebetween, for preventing the diffusion of hydrogen or water.
摘要翻译：根据本发明的半导体器件包括：形成在半导体衬底10上方并包括下电极36的铁电电容器42，形成在下电极36上的强电介质膜38和形成在强电介质膜38上的上电极40; 形成在半导体衬底10和铁电电容器42上方并具有表面平坦化的氧化硅膜60; 形成在氧化硅膜60上的形成有氧化硅膜61的平坦阻挡膜62，用于防止氢或水的扩散; 形成在阻挡膜62上方并具有平坦化表面的氧化硅膜64; 以及形成在氧化硅膜74上的形成有氧化硅膜76的平坦阻挡膜78，用于防止氢或水的扩散。

89. 发明申请

US20130244016A1 FERROELECTRIC THIN FILM HAVING SUPERLATTICE STRUCTURE, MANUFACTURING METHOD THEREOF, FERROELECTRIC ELEMENT, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有超导结构的电解薄膜，其制造方法，电磁元件及其制造方法
公开(公告)号：US20130244016A1
公开(公告)日：2013-09-19
申请号：US13878571
申请日：2011-10-04
申请人： Minoru Osada , Takayoshi Sasaki
发明人： Minoru Osada , Takayoshi Sasaki
IPC分类号： H01L41/18 , C30B19/06
CPC分类号： H01L41/183 , C30B19/062 , G11C11/22 , H01G4/12 , H01G4/33 , H01L21/02197 , H01L27/11507 , H01L28/55 , H01L41/1871 , H01L41/1873 , H01L41/1876 , H01L41/1878 , H01L41/317 , Y10T428/24975
摘要： At least two types of dielectric materials such as oxide nanosheets having a layered perovskite structure that differ from each other are laminated, and the nanosheets are bonded to each other via an ionic material, thereby producing a superlattice structure-having ferroelectric thin film. Having the layered structure, the film can exhibit ferroelectricity as a whole, though not using a ferroelectric material therein. Accordingly, there is provided a ferroelectric film based on a novel principle, which is favorable for ferroelectric memories and others and which is free from a size effect even though extremely thinned.
摘要翻译：层叠具有彼此不同的层状钙钛矿结构的氧化物纳米片的至少两种类型的电介质材料，并且通过离子材料将纳米片彼此接合，从而制造具有铁电薄膜的超晶格结构。具有层状结构，尽管在其中不使用铁电体材料，膜可以表现出铁电体的整体。因此，提供了一种基于新颖原理的铁电体膜，其有利于铁电存储器等，即使极薄也不会产生尺寸效应。

90. 发明授权

US08513130B2 Semiconductor substrate and method of fabricating semiconductor device 有权
标题翻译：半导体衬底及制造半导体器件的方法
公开(公告)号：US08513130B2
公开(公告)日：2013-08-20
申请号：US13034238
申请日：2011-02-24
申请人： Tetsuo Yaegashi
发明人： Tetsuo Yaegashi
IPC分类号： H01L21/311
CPC分类号： H01L27/11502 , H01L27/10852 , H01L27/11507 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.
摘要翻译：半导体基板包括晶片，其包括元件区域和描绘元件区域的非元件区域，位于元件区域中的第一层状结构，覆盖第一层状结构的第一绝缘膜，并且相对于蚀刻配方，覆盖元件区域中由第一绝缘膜覆盖的第一层状结构的第二绝缘膜，并且相对于蚀刻配方显示第二蚀刻速率，第二蚀刻速率大于第一蚀刻速率，以及位于所述非元件区域中的第二层状结构，其中所述第二层状结构包括所述第一层状结构的至少一部分。

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