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81. 发明申请

US20170040421A1 STRUCTURE FOR RELAXED SIGE BUFFERS INCLUDING METHOD AND APPARATUS FOR FORMING 有权
标题翻译：松散信号缓冲器的结构，包括形成方法和装置
公开(公告)号：US20170040421A1
公开(公告)日：2017-02-09
申请号：US15210030
申请日：2016-07-14
申请人： Applied Materials, Inc.
发明人： Zhiyuan YE , Errol Antonio C. SANCHEZ , Keun-Yong BAN , Xinyu BAO
IPC分类号： H01L29/267 , H01L21/02 , C23C8/02 , H01L29/06
CPC分类号： C23C8/02 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02502 , H01L21/02532 , H01L21/0262
摘要： Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.
摘要翻译：本公开的实施例提供了用于制造用于放大或切换电子信号的晶体管的半导体器件的方法和装置。具体地，本公开的实施例一般涉及具有包括半导体材料的中间层和在有源器件层下方的半导体材料的缓冲层的膜堆叠的半导体器件。在各种实施例中，中间层可以包括在硅基衬底的第一表面和缓冲层之间形成的III-V族半导体材料。在某些实施例中，缓冲层可以包括IV族半导体材料。中间层可以具有设计用于减轻IV族缓冲层和硅基底物之间的晶格失配的晶格常数。缓冲层可以提供有源器件层的改进的集成以提高所得器件的性能。

82. 发明申请

US20170033017A1 Integrated Circuit Having Strained Fins on Bulk Substrate and Method to Fabricate Same 有权
标题翻译：集成电路在散装衬底上具有应变片和制造相同的方法
公开(公告)号：US20170033017A1
公开(公告)日：2017-02-02
申请号：US15144136
申请日：2016-05-02
申请人： International Business Machines Corporation
发明人： Karthik Balakrishnan , Kangguo Cheng , Pouya Hashemi , Alexander Reznicek
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/78 , H01L29/165
CPC分类号： H01L21/823807 , H01L21/02255 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/823821 , H01L27/0924 , H01L29/165 , H01L29/7849
摘要： A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins. The third sub-set of fins is composed of a second semiconductor material that differs from the first semiconductor material. Each fin of the third subset has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set. At least one structure formed by the method is also disclosed.
摘要翻译：一种方法包括形成由第一半导体材料构成的一组鳍片。该方法进一步加热翅片集合以使翅片冷凝并引起其垂直侧壁上的一层氧化物的生长，掩蔽散热片的第一子组，通过除去第二子组而在氧化物中形成多个空隙的翅片，其中每个空隙具有三维形状和尺寸，其对应于来自第二子组的相应的去除翅片的三维形状和尺寸，并且在空隙中外延生长第三子鳍组。翅片的第三子组由与第一半导体材料不同的第二半导体材料组成。第三子集的每个鳍具有来自第二子集的相应的去除翅片的三维形状和尺寸。还公开了通过该方法形成的至少一种结构。

83. 发明授权

US09559255B2 Epitaxial structure 有权
标题翻译：外延结构
公开(公告)号：US09559255B2
公开(公告)日：2017-01-31
申请号：US14098743
申请日：2013-12-06
申请人： Tsinghua University , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： Yang Wei , Shou-Shan Fan
IPC分类号： H01L29/06 , H01L33/12 , H01L51/00 , B82Y30/00 , B82Y40/00 , C30B25/02 , C30B25/18 , C30B29/40 , H01L33/00
CPC分类号： H01L33/12 , B82Y30/00 , B82Y40/00 , C01B21/0632 , C01B32/168 , C30B25/02 , C30B25/186 , C30B29/403 , C30B29/406 , H01L21/0242 , H01L21/02422 , H01L21/02444 , H01L21/0245 , H01L21/02458 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/02598 , H01L21/0262 , H01L21/02642 , H01L21/02647 , H01L21/67109 , H01L29/0673 , H01L33/007 , H01L33/0075 , H01L33/0079 , H01L51/0048 , H01L2924/0002 , Y10S977/734 , Y10S977/742 , Y10S977/75 , Y10S977/752 , Y10S977/755 , Y10S977/788 , Y10S977/789 , Y10S977/847 , Y10S977/887 , Y10S977/932 , Y10T428/24331 , H01L2924/00
摘要： An epitaxial structure is provided. The epitaxial structure includes a substrate, an first epitaxial layer, a second epitaxial layer, a first carbon nanotube layer and a second carbon nanotube layer. The first epitaxial layer is located on the substrate. The first carbon nanotube layer is located between the substrate and the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer. The second carbon nanotube layer is located between the first epitaxial layer and the second epitaxial layer.
摘要翻译：提供外延结构。外延结构包括衬底，第一外延层，第二外延层，第一碳纳米管层和第二碳纳米管层。第一外延层位于衬底上。第一碳纳米管层位于衬底和第一外延层之间。第二外延层位于第一外延层上。第二碳纳米管层位于第一外延层和第二外延层之间。

84. 发明申请

US20170025538A1 Nanowire Field Effect Transistor Device Having a Replacement Gate 审中-公开
标题翻译：具有替代门的纳米线场效应晶体管器件
公开(公告)号：US20170025538A1
公开(公告)日：2017-01-26
申请号：US15286679
申请日：2016-10-06
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Richard Kenneth Oxland
IPC分类号： H01L29/78 , H01L29/423 , H01L29/20 , H01L29/16 , H01L29/66 , H01L29/06
CPC分类号： H01L21/0245 , B82Y10/00 , B82Y40/00 , H01L21/02458 , H01L21/02532 , H01L21/0254 , H01L21/28575 , H01L21/76224 , H01L27/0886 , H01L27/0924 , H01L27/10879 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/1033 , H01L29/1079 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/2003 , H01L29/205 , H01L29/41791 , H01L29/42376 , H01L29/42392 , H01L29/495 , H01L29/51 , H01L29/66439 , H01L29/66522 , H01L29/66545 , H01L29/66742 , H01L29/66977 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78681 , H01L29/78696 , H01L2029/7858
摘要： A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.
摘要翻译：器件包括衬底，缓冲层，纳米线，栅极结构和牺牲层的残余物。缓冲层位于衬底之上。纳米线在缓冲层之上，并且包括一对源极/漏极区域和源极/漏极区域之间的沟道区域。栅极结构围绕沟道区域。牺牲层的残余物在缓冲层和纳米线之间，并且包括III-V族半导体材料。

85. 发明申请

US20170018457A1 Semiconductor Device Comprising an Oxygen Diffusion Barrier and Manufacturing Method 有权
标题翻译：包含氧扩散屏障的半导体器件和制造方法
公开(公告)号：US20170018457A1
公开(公告)日：2017-01-19
申请号：US14801087
申请日：2015-07-16
申请人： Infineon Technologies AG
发明人： Hans-Joachim Schulze , Johannes Baumgartl
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L29/36 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/26506 , H01L21/324 , H01L21/76841 , H01L29/0615 , H01L29/155 , H01L29/161 , H01L29/165 , H01L29/7395 , H01L29/7397 , H01L29/7813 , H01L29/861 , H01L29/8611
摘要： An embodiment of a method of manufacturing a semiconductor device includes forming an oxygen diffusion barrier on a first surface of a Czochralski or magnetic Czochralski silicon substrate. A silicon layer is formed on the oxygen diffusion barrier. P-doped and n-doped semiconductor device regions are formed in the silicon layer. The method also includes forming first and second load terminal contacts.
摘要翻译：制造半导体器件的方法的一个实施例包括在切克劳斯基（Czochralski）的第一表面上形成氧扩散阻挡层，或在磁性切克劳斯基硅衬底上形成氧扩散阻挡层。在氧扩散阻挡层上形成硅层。在硅层中形成P掺杂和n掺杂的半导体器件区域。该方法还包括形成第一和第二负载端子触点。

86. 发明申请

US20170012113A1 METHOD FOR PREPARING SUBSTRATE USING GERMANIUM CONDENSATION PROCESS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME 有权
标题翻译：使用锗浓缩方法制备基材的方法和使用其制造半导体器件的方法
公开(公告)号：US20170012113A1
公开(公告)日：2017-01-12
申请号：US15115262
申请日：2015-01-27
申请人： IUCF-HYU
发明人： Jea Gun PARK , Tea Hun SHIM , Seung Hyun SONG , Du Yeong LEE
IPC分类号： H01L29/66 , H01L21/02 , H01L21/225 , H01L29/16
CPC分类号： H01L29/66795 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02532 , H01L21/02587 , H01L21/02664 , H01L21/2257 , H01L29/16 , H01L29/785 , H01L29/7854
摘要： The present invention suggests a substrate manufacturing method and a manufacturing method of a semiconductor device comprising: providing a SOI structure having an insulation layer and a silicon layer laminated on a substrate; laminating to form a silicon germanium layer and a capping silicon layer on the SOI structure; implementing oxidation process at two or more temperatures and heat treatment process at least once during the oxidation process to form a germanium cohesion layer and a silicon dioxide layer; and removing the silicon dioxide layer.
摘要翻译：本发明提出一种半导体器件的衬底制造方法和制造方法，包括：提供层叠在衬底上的绝缘层和硅层的SOI结构; 层叠以在SOI结构上形成硅锗层和覆盖硅层; 在氧化过程中在两个或多个温度下进行氧化处理和热处理工艺至少一次以形成锗内聚层和二氧化硅层; 并除去二氧化硅层。

87. 发明申请

US20170004968A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20170004968A1
公开(公告)日：2017-01-05
申请号：US15194361
申请日：2016-06-27
申请人： Applied Materials, Inc.
发明人： Xinyu BAO , Zhiyuan YE , Jean-Baptiste PIN , Errol SANCHEZ , Franck BASSANI , Thierry BARON , Yann BOGUMILOWICZ , Jean-Michel HARTMANN
IPC分类号： H01L21/02 , H01L29/201 , H01L29/06 , H01L29/04
CPC分类号： H01L21/02433 , H01L21/02381 , H01L21/0245 , H01L21/02543 , H01L21/02546 , H01L21/02549 , H01L21/0262 , H01L21/02694 , H01L29/045 , H01L29/0657 , H01L29/201
摘要： A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a plane and a plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the plane in the direction of the plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.
摘要翻译：公开了一种半导体器件，其具有半导体衬底，该半导体衬底具有具有<1,0,0>面和<1,1,0>平面的晶体结构，以及与大约0.3度至大约0.7度的角度形成的表面， <1,0,0>平面在<1,1,0>平面的方向; 以及形成在半导体衬底上的化合物半导体层。化合物半导体层没有反相边界，并且具有在约200nm和约1000nm之间的厚度。

88. 发明申请

US20160380147A1 EPITAXIAL STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：外来结构及其制造方法
公开(公告)号：US20160380147A1
公开(公告)日：2016-12-29
申请号：US15263338
申请日：2016-09-12
申请人： Tsinghua University , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： YANG WEI , SHOU-SHAN FAN
IPC分类号： H01L33/00 , H01L21/67 , C30B29/40 , C01B21/06 , C30B25/18 , H01L21/02 , C01B31/02
CPC分类号： H01L33/12 , B82Y30/00 , B82Y40/00 , C01B21/0632 , C01B32/168 , C30B25/02 , C30B25/186 , C30B29/403 , C30B29/406 , H01L21/0242 , H01L21/02422 , H01L21/02444 , H01L21/0245 , H01L21/02458 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/02598 , H01L21/0262 , H01L21/02642 , H01L21/02647 , H01L21/67109 , H01L29/0673 , H01L33/007 , H01L33/0075 , H01L33/0079 , H01L51/0048 , H01L2924/0002 , Y10S977/734 , Y10S977/742 , Y10S977/75 , Y10S977/752 , Y10S977/755 , Y10S977/788 , Y10S977/789 , Y10S977/847 , Y10S977/887 , Y10S977/932 , Y10T428/24331 , H01L2924/00
摘要： An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following steps. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein.
摘要翻译：提供外延结构及其制造方法。外延结构包括衬底，外延层和碳纳米管层。外延层位于衬底上。碳纳米管层位于外延层中。该方法包括以下步骤。提供了具有外延生长面的基板。碳纳米管层悬浮在外延生长表面上方。从外延生长表面外延生长外延层以包围其中的碳纳米管层。

89. 发明申请

US20160379895A1 FORMATION OF STRAINED FINS IN A FINFET DEVICE 有权
公开(公告)号：US20160379895A1
公开(公告)日：2016-12-29
申请号：US15263836
申请日：2016-09-13
申请人： International Business Machines Corporation
发明人： Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L21/84 , H01L29/165 , H01L21/02 , H01L27/12 , H01L21/324 , H01L21/225 , H01L29/78 , H01L29/66
CPC分类号： H01L21/845 , H01L21/02236 , H01L21/02255 , H01L21/0245 , H01L21/02532 , H01L21/02612 , H01L21/02636 , H01L21/02664 , H01L21/2251 , H01L21/2254 , H01L21/30604 , H01L21/30625 , H01L21/308 , H01L21/324 , H01L21/76224 , H01L21/76229 , H01L21/7624 , H01L27/1211 , H01L29/0653 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a semiconductor substrate, wherein the plurality of fins includes a set of fins that include a base portion that is comprised of relaxed silicon-germanium (SiGe) and an upper portion that is comprised of semiconductor material. In one aspect, a first set of one or more fins that include an upper portion comprised of a first semiconductor material. In another aspect, a second set of one or more fins that include an upper portion comprised of a second semiconductor material.

90. 发明申请

US20160372607A1 STRAIN COMPENSATION IN TRANSISTORS 有权
标题翻译：晶体管中的应变补偿
公开(公告)号：US20160372607A1
公开(公告)日：2016-12-22
申请号：US15120818
申请日：2014-03-28
申请人： INTEL CORPORATION
发明人： VAN H. LE , BENJAMIN CHU-KUNG , JACK T. KAVALIEROS , RAVI PILLARISETTY , WILLY RACHMADY , HAROLD W. KENNEL
IPC分类号： H01L29/786 , H01L29/66 , H01L29/423 , H01L29/15 , H01L29/06
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/0245 , H01L21/02461 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/02532 , H01L21/02543 , H01L21/02546 , H01L29/0673 , H01L29/1054 , H01L29/1079 , H01L29/155 , H01L29/165 , H01L29/42364 , H01L29/42392 , H01L29/66439 , H01L29/66742 , H01L29/66772 , H01L29/775 , H01L29/7849 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，包括：第一外延层，其耦合到具有第一晶格常数的衬底; 第二外延层，在第一层上，具有第二晶格常数; 第三外延层，与第二层的上表面接触，具有不等于第二晶格常数的第三晶格常数; 以及在所述第三层上的包括沟道区的外延器件层; 其中（a）第一层被松弛并且包括缺陷，（b）第二层被压缩应变并且第三层被拉伸应变，并且（c）第一层，第二层，第三层以及器件层都包括在沟槽。本文描述了其它实施例。

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