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81. 发明授权

US5834808A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5834808A
公开(公告)日：1998-11-10
申请号：US719984
申请日：1996-09-24
申请人： Masaru Tsukiji
发明人： Masaru Tsukiji
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11521 , G11C11/5621 , G11C11/5642 , G11C16/0458 , H01L27/115 , H01L29/66825 , H01L29/7887 , G11C2211/5612
摘要： The object of the present invention is to provide a non-volatile semiconductor memory device which is capable of increasing a integration density of a memory cell by increasing the number of states to be expressed with one memory cell. A non-volatile semiconductor memory device of the present invention has a structure in which two floating gates (3, 4) under one control gate (5) having a minimum dimension are provided, each of two floating gates is able to express two values in accordance with existences of stored charges whereby one memory cell is able to express four values.
摘要翻译：本发明的目的是提供一种非易失性半导体存储器件，其能够通过增加要由一个存储器单元表达的状态数来增加存储器单元的积分密度。本发明的非挥发性半导体存储器件具有这样一种结构，其中设置了具有最小尺寸的一个控制栅极（5）下方的两个浮置栅极（3,4），两个浮动栅极中的每一个能够表达两个值根据存储的电荷的存在，由此一个存储器单元能够表达四个值。

82. 发明授权

US5789777A Non-volatile memory having multi-bit data cells with double layered floating gate structure 失效
标题翻译：具有双层浮栅结构的多位数据单元的非易失性存储器
公开(公告)号：US5789777A
公开(公告)日：1998-08-04
申请号：US778410
申请日：1997-01-02
申请人： Toshiaki Kojima
发明人： Toshiaki Kojima
IPC分类号： G11C17/00 , G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0458 , H01L29/7887 , G11C2211/5612 , G11C2211/5613
摘要： The non-volatile memory has a storage cell complying with multi-bit data by means of a double layered floating gate architecture. The cell comprises: source 2 and drain 3 which are distant from each other along a direction L in a semiconductor substrate 1; a single first floating gate 4A which is provided between the source and the drain and above a principal plane of the semiconductor substrate and extends along a direction crossing the direction L; a control gate 5 which is placed between the drain ad source and above a principal plane of the first floating gate; high impurity concentration layers 21, 22 which are isolated from the source and drain in the semiconductor substrate; a plurality of second floating gates 4B.sub.1, 4B.sub.2 which respectively extend across the first floating gate and above a principal plane of the first floating gate and extend from a position different than either of the source and the drain up to a position above a principal plane of the high impurity concentration layer; and a plurality of program gates 6.sub.1, 6.sub.2 which are placed correspondingly above principal planes of the second floating gates.
摘要翻译：非易失性存储器具有通过双层浮栅结构符合多位数据的存储单元。电池包括：沿着半导体衬底1中的方向L彼此远离的源极2和漏极3; 设置在源极和漏极之间并且位于半导体衬底的主平面之上并且沿着与方向L交叉的方向延伸的单个第一浮置栅极4A; 控制门5，其设置在排水道源和第一浮动门的主平面之上; 在半导体衬底中与源极和漏极隔离的高杂质浓度层21,22; 分别延伸穿过第一浮动栅极并位于第一浮动栅极的主平面上方并从不同于源极和漏极之一的位置延伸到多于第一浮动栅极的主平面上方的位置的多个第二浮动栅极4B1,4B2，高杂质浓度层; 以及相应地设置在第二浮动门的主平面上方的多个编程门61,62。

83. 发明授权

US5754477A Differential flash memory cell and method for programming 失效
标题翻译：差分闪存单元和编程方法
公开(公告)号：US5754477A
公开(公告)日：1998-05-19
申请号：US790902
申请日：1997-01-29
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： B82B1/00 , G11C11/56 , G11C16/04 , G11C13/00
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5642 , G11C16/0441 , G11C2211/5612 , G11C2216/08
摘要： A flash memory cell. The flash memory cell includes first and second transistors. The first transistor has a control gate coupled to a word line, a drain coupled to a data line and a floating gate. The second transistor, similarly, includes a control gate coupled to the word line, a drain coupled to a second data line and a second floating gate. The first floating gate stores a state of the second transistor prior to programming of the flash memory cell. Further, the second floating gate stores a programmed state of the second transistor. A difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.
摘要翻译：闪存单元。闪存单元包括第一和第二晶体管。第一晶体管具有耦合到字线的控制栅极，耦合到数据线的漏极和浮置栅极。类似地，第二晶体管包括耦合到字线的控制栅极，耦合到第二数据线的漏极和第二浮置栅极。在闪存单元的编程之前，第一浮动栅极存储第二晶体管的状态。此外，第二浮动栅极存储第二晶体管的编程状态。第一和第二晶体管的状态之间的差异代表存储在闪存单元中的数据的值。

84. 发明授权

US5740103A Electrically programmable memory cell 失效
标题翻译：电可编程存储单元
公开(公告)号：US5740103A
公开(公告)日：1998-04-14
申请号：US812016
申请日：1997-03-06
申请人： Constantin Papadas , Bernard Guillaumot
发明人： Constantin Papadas , Bernard Guillaumot
IPC分类号： H01L21/8247 , G11C11/56 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L29/66825 , G11C11/5621 , G11C11/5635 , H01L21/2815 , H01L29/42324 , H01L29/7883 , G11C2211/5612
摘要： An electrically programmable cell comprises a substrate of the first conductivity type having a channel region, a control gate on a first insulating layer above the channel region, a source region and a drain region of a second conductivity type, on both sides of the channel region, at least the drain region including a low-doped region adjacent to the channel, a floating gate on a second insulating layer above at least a portion of said low-doped region. The thickness of the second insulating layer is lower than the thickness of the first insulating layer and is low enough for having charge transfers through tunnel effect.
摘要翻译：电可编程单元包括具有沟道区的第一导电类型的衬底，沟道区上方的第一绝缘层上的控制栅极，第二导电类型的源极区和漏极区，在沟道区的两侧至少所述漏极区域包括与所述沟道相邻的低掺杂区域，位于所述低掺杂区域的至少一部分上的第二绝缘层上的浮置栅极。第二绝缘层的厚度低于第一绝缘层的厚度，并且足够低以通过隧道效应进行电荷转移。

85. 发明授权

US5739568A Non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture and programming method for the same 失效
标题翻译：具有通过双层浮栅结构应用于多位数据的单元的非易失性存储器及其编程方法
公开(公告)号：US5739568A
公开(公告)日：1998-04-14
申请号：US563886
申请日：1995-11-21
申请人： Toshiaki Kojima
发明人： Toshiaki Kojima
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0475 , G11C11/5621 , G11C16/0458 , H01L29/7887 , G11C2211/5612 , G11C2211/5613
摘要： An object of the present invention is to contribute to increase of storage capacity of a memory. A non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture. The memory has a storage cell transistor which comprises source 2 and drain 3 being formed in a semiconductor substrate 1 distantly from each other. The storage cell transistor, furthermore comprises a single first floating gate 4A being laid between the source and drain above the semiconductor substrate, and a plurality of second floating gates 4B.sub.1 -4B.sub.n which are distant from each other and face the first floating gate. Since the second floating gates respectively store carrier corresponding to data bits and the first floating gate determines a threshold value of drain current in accordance with sum amount of carrier stored in all of the second floating gates, two or more bits data can be saved per one storage cell.
摘要翻译：本发明的目的是有助于增加存储器的存储容量。具有通过双层浮栅结构应用于多位数据的单元的非易失性存储器。存储器具有存储单元晶体管，其包括彼此远离地形成在半导体衬底1中的源极2和漏极3。存储单元晶体管还包括一个第一浮置栅极4A，其放置在半导体衬底之上的源极和漏极之间，以及多个第二浮置栅极4B1-4Bn，它们彼此远离并面向第一浮动栅极。由于第二浮动门分别存储对应于数据位的载波，并且第一浮置栅极根据存储在所有第二浮置栅极中的载波的总和量来确定漏极电流的阈值，因此可以每一个存储两个或更多位数据存储单元。

86. 发明授权

US10008511B2 Dense arrays and charge storage devices 有权
公开(公告)号：US10008511B2
公开(公告)日：2018-06-26
申请号：US15368396
申请日：2016-12-02
申请人： SANDISK TECHNOLOGIES LLC
发明人： Thomas H. Lee
IPC分类号： H01L27/11582 , G11C16/34 , H01L21/822 , H01L27/06 , H01L27/112 , H01L27/115 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11568 , H01L27/11578 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/861 , H01L27/11558 , H01L27/11526 , H01L27/11573 , H01L29/16 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/06 , H01L29/51 , G11C16/04 , H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/739 , H01L29/786 , H01L27/12 , H01L27/1158
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

87. 发明申请

US20160284395A1 2-BIT FLASH MEMORY DEVICE AND PROGRAMMING, ERASING AND READING METHODS THEREOF 审中-公开
标题翻译： 2位闪存存储器件及其编程，擦除和读取方法
公开(公告)号：US20160284395A1
公开(公告)日：2016-09-29
申请号：US14753271
申请日：2015-06-29
申请人： Jinglun Gu , Jiang Yan
发明人： Jinglun Gu , Jiang Yan
IPC分类号： G11C11/56 , H01L29/49 , H01L29/423 , H01L29/51 , H01L29/788 , H01L27/115
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0441 , G11C2211/5612 , H01L29/42328 , H01L29/42332 , H01L29/66825 , H01L29/7887
摘要： The present invention discloses a 2-bit flash memory device comprising a P-type substrate which has a source and a drain, and first and second floating gates which are successively located on the upper and lower sides of the substrate. The first and second floating gates are N-type doped polysilicon, the first control gate is P-type polysilicon, and the second control gate is N-type polysilicon. The present invention can expand the storage capacity per unit area of a floating gate flash memory, thus reducing the dimension of the floating gate flash memory.
摘要翻译：本发明公开了一种2位闪速存储器件，其包括具有源极和漏极的P型衬底以及依次位于衬底的上侧和下侧的第一和第二浮置栅极。第一和第二浮栅是N型掺杂多晶硅，第一控制栅极是P型多晶硅，第二控制栅极是N型多晶硅。本发明可以扩展浮动栅极闪存的每单位面积的存储容量，从而减小浮动栅极闪存的尺寸。

88. 发明申请

US20160079258A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20160079258A1
公开(公告)日：2016-03-17
申请号：US14856131
申请日：2015-09-16
申请人： SANDISK 3D LLC
发明人： Thomas H. Lee
IPC分类号： H01L27/115 , G11C16/10 , G11C16/26 , H01L29/861 , H01L29/423 , H01L29/51 , H01L29/06 , H01L27/112 , G11C16/14
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包含多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续级之间的至少一个表面平坦化。

89. 发明申请

US20150044833A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20150044833A1
公开(公告)日：2015-02-12
申请号：US14494320
申请日：2014-09-23
申请人： SANDISK 3D LLC
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Igor G. Kouznetsov , Mark G. Johnson , Paul Michael Farmwald
IPC分类号： H01L27/115 , H01L29/66 , H01L29/16
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

90. 发明申请

US20120223380A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 有权
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20120223380A1
公开(公告)日：2012-09-06
申请号：US13468731
申请日：2012-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

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