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81. 发明授权

US5943381A Multiple input frequency locked loop 失效
标题翻译：多输入频率锁定环路
公开(公告)号：US5943381A
公开(公告)日：1999-08-24
申请号：US850149
申请日：1997-05-02
申请人： George Phillip Zampetti
发明人： George Phillip Zampetti
IPC分类号： G06F13/00 , G01S19/22 , G01S19/37 , G04G7/00 , G04G7/02 , H03L7/08 , H03L7/087 , H03L7/093 , H03L7/14 , H04J3/06 , H03D3/24
CPC分类号： G04G7/00 , H03L7/08 , H03L7/143 , H04J3/0688 , H03L7/087
摘要： A dual locked loop is disclosed comparing preferably a GPS signal with an E1 signal and the E1 signal with the output of the loop. The GPS signal is low pass filtered to provide a low pass filtered GPS versus E1 signal that is used as a calibration for a closed loop having a second low pass filter for filtering the comparisons of the E1 and the output signal. By appropriately selecting the filter parameters, the output stability can track the stability of the local oscillator driving the NCO for short term stability, the medium term stability of the E1 signal and the long term stability of the GPS signal.
摘要翻译：公开了一种双锁定环路，其优选地将GPS信号与E1信号和E1信号与环路的输出进行比较。 GPS信号被低通滤波以提供低通滤波的GPS对E1信号，该信号用作用于具有用于滤波E1和输出信号的比较的第二低通滤波器的闭环的校准。通过适当选择滤波器参数，输出稳定性可以跟踪驱动NCO的本地振荡器的短期稳定性，E1信号的中期稳定性和GPS信号的长期稳定性的稳定性。

82. 发明授权

US5918040A Method for maintaining time synchronization between two processors in a network interface 失效
标题翻译：用于在网络接口中维护两个处理器之间的时间同步的方法
公开(公告)号：US5918040A
公开(公告)日：1999-06-29
申请号：US615813
申请日：1995-07-25
申请人： Neil Alasdair James Jarvis
发明人： Neil Alasdair James Jarvis
IPC分类号： G04G7/00 , H04J3/06 , H04L12/403 , H04L29/06 , G06F1/12
CPC分类号： G04G7/00 , H04J3/0667 , H04L29/06
摘要： A method for performing timer synchronization between a first processor having a first timer and a second processor having a second timer is presented. The first processor issues to the second processor a first timer value corresponding to the current value of the first timer and the second timer compares the first timer value with a second timer value corresponding to the current value of the second timer. If the second timer value is less than the first timer value, the second processor increments the second timer value to a new second timer value equal to the first timer value. If the second timer value is greater than the first timer value, the second processor issues to the first processors the second timer value and the first processor adjusts the first timer value to be equal to the second timer value.
摘要翻译：提出了一种用于在具有第一定时器的第一处理器和具有第二定时器的第二处理器之间执行定时器同步的方法。第一处理器向第二处理器发出与第一定时器的当前值相对应的第一定时器值，并且第二定时器将第一定时器值与对应于第二定时器的当前值的第二定时器值进行比较。如果第二定时器值小于第一定时器值，则第二处理器将第二定时器值递增到等于第一定时器值的新的第二定时器值。如果第二定时器值大于第一定时器值，则第二处理器向第一处理器发出第二定时器值，并且第一处理器将第一定时器值调整为等于第二定时器值。

83. 发明授权

US5847613A Compensation of long term oscillator drift using signals from distant hydrogen clouds 失效
标题翻译：使用远距离氢云的信号补偿长期振荡器漂移
公开(公告)号：US5847613A
公开(公告)日：1998-12-08
申请号：US877873
申请日：1997-06-18
申请人： Carl Erik Joakim Langlet , Nils Bertil Noren
发明人： Carl Erik Joakim Langlet , Nils Bertil Noren
IPC分类号： G04F5/00 , G04G7/00 , H03L7/26
CPC分类号： G04G7/00 , G04F5/00
摘要： A method and apparatus for compensating for the long term drift of an oscillator. Signals from hydrogen clouds are received and processed to generate an adjustment signal, which is used to adjust the frequency of the oscillator. The adjustment signal is derived from a frequency spectrum midpoint estimated from the signal strength of the received signals.
摘要翻译：一种用于补偿振荡器的长期漂移的方法和装置。来自氢云的信号被接收和处理以产生用于调节振荡器频率的调整信号。调整信号从根据接收信号的信号强度估计的频谱中点导出。

84. 发明授权

US5657297A Clock apparatus having high accuracy 失效
标题翻译：时钟设备具有高精度
公开(公告)号：US5657297A
公开(公告)日：1997-08-12
申请号：US378972
申请日：1995-01-27
申请人： Yasufumi Honda
发明人： Yasufumi Honda
IPC分类号： G04G19/10 , G04G7/00 , G04G19/08 , G06F1/14 , G04C11/00 , G04B1/00 , G04B9/00
CPC分类号： G04G7/00 , G04G19/08
摘要： A clock apparatus has a first clock unit, a backup power supply unit, a second clock unit, and a control unit. The first clock unit is used to count time, and the backup power supply unit is used to supply a backup power voltage to the first clock unit, when a general power supply unit does not supply a general power voltage to the clock apparatus. The second clock unit has a higher accuracy than the first clock unit. The control unit is used to adjust the time counted by the first clock unit in accordance with a specific period counted at the second clock unit, and the control unit is also used to control the resetting of an operation of the second clock unit, when the general power supply unit starts to supply the general power voltage to the clock apparatus after the general power supply unit has been stopped. Consequently, the clock apparatus has a high accuracy corresponding to the second clock unit, and has a low consumption power when the general power supply unit cannot to supply the general power voltage to the clock apparatus, so that an improved batter backup operation for the clock apparatus can be realized.
摘要翻译：时钟装置具有第一时钟单元，备用电源单元，第二时钟单元和控制单元。第一时钟单元用于计数时间，并且备用电源单元用于在一般电源单元不向时钟设备提供通用电源电压时向第一时钟单元提供备用电源电压。第二时钟单元具有比第一时钟单元更高的精度。控制单元用于根据在第二时钟单元计数的特定周期来调整由第一时钟单元计数的时间，并且控制单元还用于控制第二时钟单元的操作的复位，当一般电源单元停止后，一般电源单元开始向时钟装置提供一般电源电压。因此，时钟装置具有对应于第二时钟单元的高精度，并且当一般电源单元不能向时钟装置提供一般电源电压时，具有低功耗，从而改善了对时钟的电池备份操作装置可以实现。

85. 发明授权

US5469467A Method for synchronizing the reference frequency oscillator of a metallic-based microcell to a master oscillator 失效
标题翻译：一种将基于金属的微小区的参考频率振荡器与主振荡器同步的方法
公开(公告)号：US5469467A
公开(公告)日：1995-11-21
申请号：US138583
申请日：1993-10-15
申请人： George P. Vella-Coleiro
发明人： George P. Vella-Coleiro
IPC分类号： H04B7/26 , G04G7/00 , H03L7/00 , H04Q7/36 , H04L7/00 , H04B7/00
CPC分类号： H03L7/00 , G04G7/00 , H04J3/0638
摘要： The present invention involves a device for synchronizing the broadcast frequency of a base station and a microcell linked together by a metallic medium as well as a method for using the device to synchronize the base oscillator and the microcell oscillator. The device comprises a base transmitter which transmits a base time-of-day signal to a microcell comparer, and a microcell clock which sends a microcell time-of-day signal to the microcell comparer. A microcell oscillator provides the microcell clock with a reference frequency. The microcell comparer calculates a time difference which represents a time difference between the base time-of-day signal and the microcell time-of-day signal. The microcell comparer then outputs a correction signal to a digital controller. The digital controller adjusts a microcell oscillator according to the correction signal.
摘要翻译：本发明涉及一种用于使基站的广播频率和由金属介质链接在一起的微小区同步的装置，以及使用该装置同步基站振荡器和微小区振荡器的方法。该设备包括：基本发射机，其将基本时钟信号发送到微小区比较器，以及将小区时间信号发送到微小区比较器的微小区时钟。微小区振荡器为微小区时钟提供参考频率。微单元比较器计算表示基准时刻信号与微小时隙日信号之间的时间差的时间差。然后，微小区比较器将校正信号输出到数字控制器。数字控制器根据校正信号调整微小区振荡器。

86. 发明授权

US5276661A Master clock generator for a parallel variable speed constant frequency power system 失效
标题翻译：主时钟发生器并联变频恒频电源系统
公开(公告)号：US5276661A
公开(公告)日：1994-01-04
申请号：US553514
申请日：1990-07-18
申请人： Mirza A. Beg
发明人： Mirza A. Beg
IPC分类号： G04G7/00 , H03L7/093 , H03L7/14 , G04F5/00
CPC分类号： H03L7/093 , G04G7/00 , H03L7/143
摘要： A master clock generator for a variable speed constant frequency electric power system includes a frequency select circuit for selecting an external or internal frequency reference signal and a phase comparator for producing a phase error signal representative of the phase difference between the frequency reference signal and an output clock signal. The phase error signal is combined with a control signal to produce an adjusted phase error signal. This adjusted phase error signal is integrated and a voltage control oscillator is used to produce the output signal in response to the integrated adjusted phase error signal. The control signal introduces a desired phase error between the reference signal and the output signal. Clamping circuits are provided to limit the maximum and minimum magnitudes of the integrated adjusted phase error signal, thereby limiting the maximum and minimum frequencies of the output clock signal.
摘要翻译：用于变速恒频电力系统的主时钟发生器包括用于选择外部或内部频率参考信号的频率选择电路和用于产生表示频率参考信号和输出之间的相位差的相位误差信号的相位比较器时钟信号。相位误差信号与控制信号组合以产生调整后的相位误差信号。该调整的相位误差信号被积分，并且使用压控振荡器来响应于积分调整的相位误差信号产生输出信号。控制信号在参考信号和输出信号之间引入期望的相位误差。提供钳位电路以限制积分调整的相位误差信号的最大和最小幅度，从而限制输出时钟信号的最大和最小频率。

87. 发明授权

US5276659A Clock synchronous system for a network station 失效
标题翻译：网络站的时钟同步系统
公开(公告)号：US5276659A
公开(公告)日：1994-01-04
申请号：US684212
申请日：1991-04-12
申请人： Koji Kotaki
发明人： Koji Kotaki
IPC分类号： H04L7/00 , G04C9/04 , G04G5/00 , G04G7/00 , G06F1/14 , G04B47/00 , G04C11/00 , G08B1/00
CPC分类号： G06F1/14 , G04G7/00
摘要： A clock synchronous system which secures time synchronization in a network station including a master station and a plurality of slave stations. The system monitors, at all time, a time difference between a reference time of the master station and a present time of the slave station. When the time difference exceeds a predetermined value, the system divides that time difference by a predetermined correction number to find a time correction coefficient and gradually corrects the time difference of the slave station by the time corrections coefficient.
摘要翻译：一种时钟同步系统，其在包括主站和多个从站的网络站中确保时间同步。该系统随时监视主站的基准时间与从站的当前时间之间的时间差。当时间差超过预定值时，系统将该时间差除以预定的校正次数以找到时间校正系数，并逐渐地将从站的时间差校正为时间校正系数。

88. 发明授权

US5204845A Clock synchronization 失效
标题翻译：时钟同步
公开(公告)号：US5204845A
公开(公告)日：1993-04-20
申请号：US691002
申请日：1991-06-18
申请人： Evan J. Stanbury , Peter G. Jeremy
发明人： Evan J. Stanbury , Peter G. Jeremy
IPC分类号： G04G3/02 , G04G7/00 , G06F1/14
CPC分类号： G04G7/00
摘要： A method of adjusting the pulse rate of a local clock (1) by generating a first pulse train at a first predetermined rate, dividing the pulse train by a divisor (3) to produce a second pulse train. The value of the divisor (3) is selected (4,5,6) so that the rate of the second pulse train is adjusted within a predetermined range.
摘要翻译： PCT No.PCT / AU89 / 00492 Sec。 371日期1991年6月18日 102（e）日期1991年6月18日PCT提交1989年11月17日PCT公布。公开号WO90 / 07147 日期：1982年6月28日。一种通过以第一预定速率产生第一脉冲序列来调整本地时钟（1）的脉率的方法，用除数（3）将脉冲序列除以产生第二脉冲串。选择除数（3）的值（4,5,6），使得第二脉冲串的速率在预定范围内被调整。

89. 发明授权

US4707142A Master clock system for a parallel variable speed constant frequency power system 失效
标题翻译：并联变频恒频电源系统主时钟系统
公开(公告)号：US4707142A
公开(公告)日：1987-11-17
申请号：US938652
申请日：1986-12-05
申请人： Donal E. Baker , Mirza A. Beg
发明人： Donal E. Baker , Mirza A. Beg
IPC分类号： G05F1/00 , G04G7/00 , H02J3/38 , H03L7/00 , G04C11/00 , H02J1/00
CPC分类号： H02J3/38 , G04G7/00 , Y10T307/735
摘要： A clock control system for a multiple channel electric power system includes a master clock circuit and control circuitry in each parallel connected channel. The channel control circuits are intially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.

90. 发明授权

US4635266A Active dispersion control for a Doppler broadened laser 失效
标题翻译：多普勒扩展激光器的主动色散控制
公开(公告)号：US4635266A
公开(公告)日：1987-01-06
申请号：US680432
申请日：1984-12-11
申请人： Roger L. Facklam
发明人： Roger L. Facklam
IPC分类号： G04G7/00 , H01S3/083 , H01S3/134 , H01S3/139 , H01S3/13
CPC分类号： G04G7/00 , H01S3/083 , H01S3/134 , H01S3/1394
摘要： A method of controlling the output of a laser in a laser clock to compensate for changes in the output of the laser due to optical dispersion resulting from laser aging and changes in laser temperature is described, which comprises, comparing the output frequency of the laser clock with a standard of known frequency, such as an atomic clock, calculating the change in laser discharge current corresponding to any difference between the laser clock frequency and the standard required to adjust the laser clock frequency to a predetermined frequency value, and adjusting the laser discharge current to a value corresponding to the predetermined laser clock frequency.
摘要翻译：描述了一种控制激光时钟中的激光输出以补偿激光老化引起的光学色散和激光温度变化引起的激光器输出变化的方法，其包括：比较激光时钟的输出频率以诸如原子钟的已知频率的标准计算激光放电电流的变化，其对应于激光时钟频率与将激光器时钟频率调整到预定频率值所需的标准之间的任何差异，并且调整激光放电电流达到对应于预定激光器时钟频率的值。

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