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81. 发明授权

US5942446A Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer 失效
标题翻译：用于形成图案化含硅介电层的氟碳聚合物层沉积主要预蚀刻等离子体蚀刻方法
公开(公告)号：US5942446A
公开(公告)日：1999-08-24
申请号：US928235
申请日：1997-09-12
申请人： Chao-Cheng Chen , Chen-Hua Yu
发明人： Chao-Cheng Chen , Chen-Hua Yu
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76802
摘要： A method for forming a patterned silicon containing dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon containing dielectric layer. There is then formed upon the silicon containing dielectric layer a hard mask layer, where the hard mask layer leaves exposed a portion of the silicon containing dielectric layer. There is then etched partially through a first plasma etch method the silicon containing dielectric layer to form a partially etched silicon containing dielectric layer. The first plasma etch method employs a first etchant gas composition comprising a first fluorocarbon etchant gas which predominantly forms a fluoropolymer layer upon at least the hard mask layer. Finally, there is then etched through a second plasma etch method the partially etched silicon containing dielectric layer to form a patterned silicon containing dielectric layer. The second plasma etch method employs a second etchant gas composition comprising a second fluoro etchant gas which predominantly etches the partially etched silicon containing dielectric layer in forming the patterned silicon containing dielectric layer.
摘要翻译：一种用于在微电子制造中形成图案化含硅介电层的方法。首先提供了在微电子制造中使用的衬底。然后在衬底上形成含硅介电层。然后在含硅电介质层上形成硬掩模层，其中硬掩模层离开暴露一部分含硅电介质层。然后通过第一等离子体蚀刻方法将含硅介电层部分地蚀刻以形成部分蚀刻的含硅介电层。第一等离子体蚀刻方法采用第一蚀刻剂气体组合物，其包括在至少硬掩模层上主要形成含氟聚合物层的第一碳氟化合物蚀刻剂气体。最后，然后通过第二等离子体蚀刻方法蚀刻部分蚀刻的含硅介电层，以形成图案化的含硅介电层。第二等离子体蚀刻方法采用包含第二氟蚀刻剂气体的第二蚀刻剂气体组合物，其主要在形成图案化的含硅介电层时蚀刻部分蚀刻的含硅介电层。

82. 发明授权

US5807789A Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI) 失效
标题翻译：用于形成具有锥形轮廓和圆角的浅沟槽的方法用于应用浅沟槽隔离（STI）
公开(公告)号：US5807789A
公开(公告)日：1998-09-15
申请号：US821353
申请日：1997-03-20
申请人： Chao-Cheng Chen , C. S. Tsai , C. H. Yu
发明人： Chao-Cheng Chen , C. S. Tsai , C. H. Yu
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3065 , H01L21/76232 , Y10S438/978
摘要： The present invention is a method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI). This invention utilizes a multiple-step dry etching process with reduced RF power and increased pressure to etch a shallow trench. This takes advantage of different degree of polymer deposition in different steps by varing the pressure and the RF power. Thus, a shallow trench with tapered profile and round corners is achieved.
摘要翻译：本发明是用于形成具有锥形轮廓和圆角的浅沟槽的方法，用于应用浅沟槽隔离（STI）。本发明利用具有降低的RF功率和增加的压力来蚀刻浅沟槽的多级干蚀刻工艺。这通过改变压力和RF功率在不同步骤中利用不同程度的聚合物沉积。因此，实现了具有锥形轮廓和圆角的浅沟槽。

83. 发明授权

US08735252B2 Method of semiconductor integrated circuit fabrication 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US08735252B2
公开(公告)日：2014-05-27
申请号：US13490635
申请日：2012-06-07
申请人： Weibo Yu , Ming-Hsi Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Ming-Hsi Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , H01L29/66795
摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.
摘要翻译：公开了制造半导体IC的方法。该方法包括接收设备。该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

84. 发明授权

US08409964B2 Shallow trench isolation with improved structure and method of forming 有权
标题翻译：浅沟隔离具有改进的结构和成型方法
公开(公告)号：US08409964B2
公开(公告)日：2013-04-02
申请号：US13399488
申请日：2012-02-17
申请人： Jhon-Jhy Liaw , Chao-Cheng Chen , Chia-Wei Chang
发明人： Jhon-Jhy Liaw , Chao-Cheng Chen , Chia-Wei Chang
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76232
摘要： A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.
摘要翻译：公开了浅沟槽隔离（STI）结构和形成STI结构的方法。实施例是形成半导体结构的方法。该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。凹部的底面通过第一材料露出，凹部的底面具有第一宽度。加宽的凹部具有第二宽度。第二宽度大于第一宽度。

85. 发明授权

US08120094B2 Shallow trench isolation with improved structure and method of forming 有权
标题翻译：浅沟隔离具有改进的结构和成型方法
公开(公告)号：US08120094B2
公开(公告)日：2012-02-21
申请号：US11838666
申请日：2007-08-14
申请人： Jhon-Jhy Liaw , Chao-Cheng Chen , Chia-Wei Chang
发明人： Jhon-Jhy Liaw , Chao-Cheng Chen , Chia-Wei Chang
IPC分类号： H01L29/94 , H01L29/76 , H01L31/062 , H01L31/119 , H01L31/113
CPC分类号： H01L21/823878 , H01L21/76232
摘要： A shallow trench isolation (STI) structure has a top portion tapering in width from wide to narrow in a direction from a substrate surface, from a first width at a top of the first portion to a second width at a bottom of the first portion. The STI structure also includes a bottom portion below the top portion, which expands from the bottom of the top portion to a substantially widened lateral distance having a third width. The third width is, in general, substantially larger than the second width. The inventive STI structure can provide desired isolation characteristics with a significantly reduced aspect ratio, thus suitable for device isolations in advanced processing technology.
摘要翻译：浅沟槽隔离（STI）结构具有在从基板表面的方向上从宽到窄的宽度从第一部分的顶部处的第一宽度到第一部分的底部处的第二宽度的顶部部分。 STI结构还包括在顶部下方的底部，其从顶部的底部膨胀到具有第三宽度的基本上加宽的横向距离。通常，第三宽度基本上大于第二宽度。本发明的STI结构可以提供期望的隔离特性，具有显着减小的纵横比，因此适用于先进加工技术中的器件隔离。

86. 发明申请

US20060151430A1 Method and system for processing multi-layer films 有权
标题翻译：多层膜加工方法及系统
公开(公告)号：US20060151430A1
公开(公告)日：2006-07-13
申请号：US11358393
申请日：2006-02-21
申请人： Hui Yang , Miao-Ju Hsu , Chao-Cheng Chen , Hun-Jan Tao
发明人： Hui Yang , Miao-Ju Hsu , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： G01L21/30 , G01R31/00
CPC分类号： H01L21/31116 , H01J37/32935 , H01L22/26
摘要： A method of processing multi-layer films, the method including: (1) processing a plurality of layers according to selected parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the processing of the associated one of the plurality of layers, and (3) determining dynamic processing progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the processing.
摘要翻译：一种处理多层薄膜的方法，该方法包括：（1）根据选定的参数处理多个层，（2）确定多个光学特性，每个光学特性与多个层之一相关联，并在处理过程中确定所述多个层中的相关联的一个层，以及（3）基于与经历所述处理的所述多个层中的特定一个层相关联的所述多个光学特性中的一个来确定动态处理进度。

87. 发明授权

US07067433B2 Method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment 失效
标题翻译：通过后期高阴极温度等离子体处理来减少Al / Al-Cu焊盘上的氟污染的方法
公开(公告)号：US07067433B2
公开(公告)日：2006-06-27
申请号：US10706382
申请日：2003-11-12
申请人： Wen-Jui Fu , Shang-Ru Shen , Yun-Hung Shen , Chao-Cheng Chen
发明人： Wen-Jui Fu , Shang-Ru Shen , Yun-Hung Shen , Chao-Cheng Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/31116 , H01L21/02046
摘要： A method of reducing fluorine contamination on a integrated circuit wafer surface is achieved. The method comprises placing an integrated circuit wafer on a cathode stage. The integrated circuit wafer comprises a surface contaminated with fluorine. The integrated circuit wafer is plasma treated with a plasma comprising a reducing gas that forms HF from the fluorine and a bombardment gas that removes the fluorine from the surface. The cathode stage is heated to thereby increase the rate of the fluorine removal.
摘要翻译：实现了降低集成电路晶片表面上的氟污染的方法。该方法包括将集成电路晶片放置在阴极级上。集成电路晶片包括被氟污染的表面。集成电路晶片用包括从氟形成HF的还原气体的等离子体等离子体处理，以及从表面除去氟的轰击气体。加热阴极级，从而提高除氟率。

88. 发明授权

US07022610B2 Wet cleaning method to eliminate copper corrosion 失效
标题翻译：湿法清洗方法消除铜腐蚀
公开(公告)号：US07022610B2
公开(公告)日：2006-04-04
申请号：US10743979
申请日：2003-12-22
申请人： Chun-Li Chou , Yih-Ann Lin , Yi-Chen Huang , Chao-Cheng Chen , Hun-Jan Tao
发明人： Chun-Li Chou , Yih-Ann Lin , Yi-Chen Huang , Chao-Cheng Chen , Hun-Jan Tao
IPC分类号： H01L21/302
CPC分类号： H01L21/02071 , H01L21/02063 , H01L21/76807
摘要： A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.
摘要翻译：用于清洁半导体衬底的方法包括使用不大于350rpm的旋转速度的去离子水清洁操作。清洁方法可以包括附加的清洁操作，例如有机清洁剂，水性化学清洁剂或去离子水/臭氧清洁剂。在完成了在含Cu导电材料和环境之间暴露单个膜的蚀刻过程结束之前，清洁方法可用于清洁衬底。去离子水清洁操作的旋转速度可防止由于将含Cu导电材料与环境分离的膜破裂导致铜腐蚀。

89. 发明授权

US06995085B2 Underlayer protection for the dual damascene etching 有权
标题翻译：双镶嵌蚀刻的底层保护
公开(公告)号：US06995085B2
公开(公告)日：2006-02-07
申请号：US10346384
申请日：2003-01-17
申请人： Lawrence Lui , Chia-Shia Tsai , Chao-Cheng Chen , Jen-Cheng Liu
发明人： Lawrence Lui , Chia-Shia Tsai , Chao-Cheng Chen , Jen-Cheng Liu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808
摘要： A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.
摘要翻译：一种在双镶嵌沟槽中保护底层扩散阻挡层的方法，以及通过蚀刻工艺与负性光致抗蚀剂的涂层。双镶嵌工艺从金属间电介质（IMD）层中的通孔蚀刻开始。接下来，沉积和图案化薄膜阻挡层以填充通孔的底部。关键的工艺步骤是负性光致抗蚀剂的涂层，其被暴露和显影以部分填充通孔。通孔中的这种厚的负光致抗蚀剂层保护了薄的扩散阻挡层免于后续的双镶嵌蚀刻加工。

90. 发明授权

US06809028B2 Chemistry for liner removal in a dual damascene process 有权
公开(公告)号：US06809028B2
公开(公告)日：2004-10-26
申请号：US10282386
申请日：2002-10-29
申请人： Chao-Cheng Chen , Chien-Chung Fu
发明人： Chao-Cheng Chen , Chien-Chung Fu
IPC分类号： H01L214763
CPC分类号： H01L21/76801 , H01L21/31056 , H01L21/76807
摘要： An improved and new process for fabricating dual damascene copper, in which trench/via liner removal from porous low-k dielectric, is performed using a new RIE chemistry of CF4/H2, to etch SiN and SiC liners. Prior to the new process, convention liner etching produced the following deleterious results: a) Cu re-deposition by sputtering, b) polymer deposits, and c) surface roughening of the porous low-k IMD dielectric. Process details are: CF4/H2 based with approximate gas flow ratios of greater than 10 to 1, hydrogen to carbon tetra-fluoride. A nominal flow ratio of 300 to 20, hydrogen to carbon tetra-fluoride, or 15 to 1, was developed.

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