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    • 85. 发明申请
    • Ferroelectric Memory and Semiconductor Memory
    • 铁电存储器和半导体存储器
    • US20060193162A1
    • 2006-08-31
    • US11382098
    • 2006-05-08
    • Ryu OgiwaraDaisaburo TakashimaSumio TanakaYukihito OowakiYoshiaki Takeuchi
    • Ryu OgiwaraDaisaburo TakashimaSumio TanakaYukihito OowakiYoshiaki Takeuchi
    • G11C11/22
    • G11C11/22
    • A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
    • 链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元,连接到存储单元单元的电极的板线,连接到存储单元单元的另一个电极的位线 通过开关晶体管,放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。 作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值 电压和比较放大。 利用这些特征,存储单元中的累积电荷的减小减少,并且在读/写操作期间阻止了干扰的发生。
    • 87. 发明申请
    • Semiconductor integrated circuit device and data write method thereof
    • 半导体集成电路器件及其数据写入方法
    • US20050232067A1
    • 2005-10-20
    • US10879297
    • 2004-06-30
    • Yoshiaki Takeuchi
    • Yoshiaki Takeuchi
    • G11C11/401G11C8/00G11C8/06G11C8/08G11C11/22G11C11/403G11C11/407
    • G11C11/22G11C8/06G11C8/08G11C11/40615
    • A semiconductor integrated circuit device includes a memory cell array, an address transition detecting circuit which detects transition of a column address signal, the column address signal being used to specify a column address of the memory cell array, a control circuit having a timeout circuit, the control circuit which generates an internal circuit control signal of desired length used to control column access to the memory cell array based on a result of detection by the address transition detecting circuit, and a column selection line whose selection time is controlled by the control circuit, wherein the column address signal used for selection of the column selection line is latched in a period of time in which the column selection line is selected at a write operation time.
    • 半导体集成电路装置包括存储单元阵列,检测列地址信号的转换的地址转换检测电路,用于指定存储单元阵列的列地址的列地址信号,具有超时电路的控制电路, 所述控制电路根据所述地址转换检测电路的检测结果生成用于控制对所述存储单元阵列的列访问的期望长度的内部电路控制信号;以及列选择线,其选择时间由所述控制电路 其中,用于选择列选择线的列地址信号在写入操作时间选择列选择线的时间段中被锁存。
    • 88. 发明申请
    • Plasma processing system and its substrate processing process, plasma enhanced chemical vapor deposition system and its film deposition process
    • 等离子体处理系统及其基板加工工艺,等离子体增强化学气相沉积系统及其薄膜沉积工艺
    • US20050223990A1
    • 2005-10-13
    • US10519475
    • 2003-10-01
    • Keisuke KawamuraAkira YamadaHiroshi MashimaKenji TagashiraYoshiaki Takeuchi
    • Keisuke KawamuraAkira YamadaHiroshi MashimaKenji TagashiraYoshiaki Takeuchi
    • H05H1/46B01J19/08C23C16/509H01J37/32H01L21/205C23C16/00
    • H01J37/32082C23C16/509H01J37/32183H01J37/32541
    • An object is to provide apparatuses for plasma processing which can make the distribution of the film thickness of a substance on a substrate uniform, methods of processing a substrate therewith, apparatuses for plasma-enhanced chemical vapor deposition, and methods for film formation therewith. When a desired substance is vapor deposited on the surface of a substrate (3), characteristics of the distribution of the thickness of a film on the substrate having a large area are improved by eliminating local imbalance in the distribution of the film thickness originating from deviation in the distribution of voltage on the ladder electrode (2), by way of adjusting impedance matching between each coaxial cable and corresponding feeding point for the ladder-shaped electrode (2) using branch cables provided to the coaxial cables for supplying high-frequency electric power to a ladder-shaped electrode (2) so as to make the film thickness uniform in the direction at right angles with the direction of fed electric power, whereby high-frequency electric power which is fed to each longitudinal electrode rod (2a) of the ladder-shaped electrode (2) can be adjusted, and distribution of voltage at a right or left part of the substrate and distribution of voltage at a central part of the substrate can be balanced, as well as by way of promoting uniformity in the distribution of the film thickness in the direction of fed electric power, by supplying streams of high-frequency electric power having the same frequency from two power supplies to the ladder-shaped electrode (2) with the phase difference between the high-frequency electric powers being varied over time.
    • 目的在于提供能够使基板上的物质的膜厚分布均匀的等离子体处理装置,用于处理基板的方法,等离子体增强化学气相沉积的装置及其成膜方法。 当在基板(3)的表面上气相沉积所需物质时,通过消除由于偏差导致的膜厚度分布的局部不平衡,改善了具有大面积的基板上的膜的厚度分布特性 在梯形电极(2)上的电压分配中,通过使用提供给用于提供高频电气的同轴电缆的分支电缆来调节每个同轴电缆与梯形电极(2)的相应馈电点之间的阻抗匹配 向梯形电极(2)施加电力以使膜厚度与与馈送电力方向成直角的方向均匀,由此,供给到每个纵向电极棒(2a)的高频电力 可以调节梯形电极(2),并且可以调整基板的右侧或左侧的电压分布以及中心部分的电压分布 可以通过将来自两个电源的具有相同频率的高频电力的流提供给梯子,从而通过提高膜馈送电力方向上的膜厚分布的均匀性来平衡基板 形状的电极(2),其中高频电功率之间的相位差随时间变化。