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81. 发明申请

US20120126307A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20120126307A1
公开(公告)日：2012-05-24
申请号：US12949092
申请日：2010-11-18
申请人： GUAN-WEI WU , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： GUAN-WEI WU , I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/76232
摘要： A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers.The charge storage structure is disposed on the substrate. The gate is disposed on the charge storage structure. The spacers are disposed on the sidewalls of the gate and the charge storage structure. The first doped region and the second doped region are respectively disposed in the substrate at two sides of the charge storage structure and at least located under the spacers. The isolation structures are respectively disposed in the substrate at two sides of the gate structure.
摘要翻译：提供了一种非易失性存储器及其制造方法。非易失性存储器包括衬底，栅极结构，第一掺杂区，第二掺杂区和一对隔离结构。栅极结构设置在基板上。栅极结构包括电荷存储结构，栅极和间隔物。电荷存储结构设置在基板上。栅极设置在电荷存储结构上。间隔件设置在栅极和电荷存储结构的侧壁上。第一掺杂区域和第二掺杂区域分别设置在电荷存储结构的两侧的基板中，并且至少位于间隔物之下。隔离结构分别设置在栅极结构的两侧的基板中。

82. 发明授权

US08093665B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08093665B2
公开(公告)日：2012-01-10
申请号：US12467479
申请日：2009-05-18
申请人： I-Chen Yang , Guan-Wei Wu , Yao-Wen Chang , Tao-Cheng Lu
发明人： I-Chen Yang , Guan-Wei Wu , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/66636 , H01L29/665 , H01L29/7834
摘要： A semiconductor device is described, which includes a substrate, a gate structure, doped regions and lightly doped regions. The substrate has a stepped upper surface, which includes a first surface, a second surface and a third surface. The second surface is lower than the first surface. The third surface connects the first surface and the second surface. The gate structure is disposed on the first surface. The doped regions are configured in the substrate at both sides of the gate structure and under the second surface. The lightly doped regions are configured in the substrate between the gate structure and the doped regions, respectively. Each lightly doped region includes a first part and a second part connecting with each other. The first part is disposed under the second surface, and the second part is disposed under the third surface.
摘要翻译：描述了一种半导体器件，其包括衬底，栅极结构，掺杂区域和轻掺杂区域。基板具有阶梯状的上表面，其包括第一表面，第二表面和第三表面。第二表面低于第一表面。第三表面连接第一表面和第二表面。栅极结构设置在第一表面上。掺杂区域在栅极结构的两侧和第二表面的下方在衬底中配置。轻掺杂区域分别配置在栅极结构和掺杂区域之间的衬底中。每个轻掺杂区域包括彼此连接的第一部分和第二部分。第一部分设置在第二表面下方，第二部分设置在第三表面下。

83. 发明申请

US20110216454A1 ELECTROSTATIC DISCHARGE PROTECTORS HAVING INCREASED RC DELAYS 有权
标题翻译：静电放电保护器增加了RC延迟
公开(公告)号：US20110216454A1
公开(公告)日：2011-09-08
申请号：US12719577
申请日：2010-03-08
申请人： Shih-Yu Wang , Chia-Ling Lu , Yu-Lien Liu , Yan-Yu Chen , Che-Shih Lin , Tao-Cheng Lu
发明人： Shih-Yu Wang , Chia-Ling Lu , Yu-Lien Liu , Yan-Yu Chen , Che-Shih Lin , Tao-Cheng Lu
IPC分类号： H02H9/04 , H03H11/26
CPC分类号： H02H9/04 , H03H11/26
摘要： An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.
摘要翻译：描述了一种用于提供静电放电（ESD）保护的RC延迟电路。电路使用NMOS晶体管和PMOS晶体管，使用相对小的电路布局面积产生大的有效电阻。

84. 发明申请

US20110080784A1 NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF 有权
标题翻译：非易失性存储器及其操作方法
公开(公告)号：US20110080784A1
公开(公告)日：2011-04-07
申请号：US12574093
申请日：2009-10-06
申请人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
发明人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
IPC分类号： G11C16/04 , G11C16/34 , G11C16/26 , G11C16/10
CPC分类号： G11C16/3468 , G11C16/0466 , G11C16/10
摘要： An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1st level and an auxiliary level respectively according to the 1st threshold-voltage distribution curve and a threshold-voltage auxiliary curve when the first and the second storage positions are programmed to the 1st and Nth levels; and programming the first and the second storage positions to the ith level according to the ith threshold-voltage distribution curve when the first and the second storage positions are not to be programmed to the 1st and Nth levels, wherein i is an integer and 1≦i≦N.
摘要翻译：提供适用于具有第一存储位置和第二存储位置的多级单元的非易失性存储器的操作方法。操作方法包括：设置N个阈值电压分布曲线，其中N个阈值电压分布曲线对应于N个电平，N是大于2的整数; 当第一和第二存储位置被编程到第1和第N级时，根据第一阈值电压分布曲线和阈值电压辅助曲线分别将第一和第二存储位置编程到第一级和辅助级; 以及当所述第一和第二存储位置不被编程到所述第一和第N电平时，根据所述第i阈值电压分布曲线将所述第一和第二存储位置编程为第i级，其中i是整数和1＆nlE; 我＆nlE; N。

85. 发明申请

US20100314680A1 MEMORY ARRAY 有权
标题翻译：内存阵列
公开(公告)号：US20100314680A1
公开(公告)日：2010-12-16
申请号：US12862020
申请日：2010-08-24
申请人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
发明人： I-Chen Yang , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L21/76885 , H01L27/11568 , H01L29/4234
摘要： A memory array includes a charge storage structure and a plurality of conductive materials over the charge storage structure is provided. Each conductive material, serving as a word line, has a substantially arc-sidewall and a substantially straight sidewall.
摘要翻译：存储器阵列包括电荷存储结构，并且提供了电荷存储结构上的多个导电材料。用作字线的每个导电材料具有基本上弧形的侧壁和基本上直的侧壁。

86. 发明授权

US07830707B2 Method of reading dual-bit memory cell 有权
标题翻译：读取双位存储单元的方法
公开(公告)号：US07830707B2
公开(公告)日：2010-11-09
申请号：US11905211
申请日：2007-09-28
申请人： Yao-Wen Chang , Tao-Cheng Lu
发明人： Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/28
摘要： A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value.
摘要翻译：读取双位存储单元的方法包括控制终端，第一终端和第二终端。双位存储单元分别具有第一位存储节点和靠近第一终端和第二终端的第二位存储节点。首先，分别对控制端子和第一端子施加控制电压和读取电压。第二端子接地以测量第一端子的第一输出电流值。然后，控制电压和读取电压分别施加到控制端子和第二端子。第一端子接地以测量第二端子的第二输出电流值。之后，根据第一输出电流值和第二输出电流值同时读取第一位存储节点的位状态和第二位存储节点的位状态。

87. 发明授权

US07692968B2 Operation method of non-volatile memory and method of improving coupling interference from nitride-based memory 有权
标题翻译：非易失性存储器的操作方法和改善氮化物存储器耦合干扰的方法
公开(公告)号：US07692968B2
公开(公告)日：2010-04-06
申请号：US11782149
申请日：2007-07-24
申请人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
发明人： Yao-Wen Chang , Guan-Wei Wu , Tao-Cheng Lu
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/26
摘要： An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.
摘要翻译：提供了一种非易失性存储器的操作方法。操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线到所选存储单元的另一侧。本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

88. 发明授权

US06683352B2 Semiconductor device structure 有权
标题翻译：半导体器件结构
公开(公告)号：US06683352B2
公开(公告)日：2004-01-27
申请号：US10078314
申请日：2002-02-15
申请人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
发明人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： H01L2976
CPC分类号： H01L21/823425 , H01L21/823443 , H01L29/4238 , H01L29/665
摘要： A metal oxide semiconductor field effect transistor structure is disclosed. A p-shape gate, disposed over a semiconductor substrate. A gate dielectric layer is disposed in between the p-shape gate and the semiconductor substrate. A drain region is disposed within the semiconductor substrate, wherein the drain region is surrounded by the p-shape gate. A source region is disposed within the semiconductor substrate, wherein the source region surrounds the p-shape gate. A silicide structure is disposed on the source/drain regions and the p-shape gate.
摘要翻译：公开了一种金属氧化物半导体场效应晶体管结构。 p型栅极，设置在半导体衬底上。栅极电介质层设置在p型栅极和半导体衬底之间。漏极区域设置在半导体衬底内，其中漏极区域被p型栅极包围。源极区域设置在半导体衬底内，其中源极区域围绕p形栅极。在源极/漏极区域和p形栅极上设置硅化物结构。

89. 发明授权

US06661273B1 Substrate pump circuit and method for I/O ESD protection 有权
标题翻译：基板泵电路和I / O ESD保护方法
公开(公告)号：US06661273B1
公开(公告)日：2003-12-09
申请号：US10225160
申请日：2002-08-22
申请人： Chun-Hsiang Lai , Meng-Huang Liu , Shin Su , Tao-Cheng Lu
发明人： Chun-Hsiang Lai , Meng-Huang Liu , Shin Su , Tao-Cheng Lu
IPC分类号： H03K508
CPC分类号： H01L27/0277 , H03K5/08
摘要： A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.
摘要翻译：用于I / O ESD保护的衬底泵电路和方法，包括连接到I / O焊盘和内部电路之间的互连的NMOS指状包括连接到I / O焊盘和内部电路与衬底之间的互连的MOS器件在I / O焊盘处于ESD应力下时，在开关控制下将其导通以通过衬底电阻器进行泵浦电流，从而上升与NMOS指状物相邻的衬底的电位，从而减少的NMOS手指的触发电压。

90. 发明授权

US06549029B1 Circuit and method for measuring capacitance 有权
标题翻译：用于测量电容的电路和方法
公开(公告)号：US06549029B1
公开(公告)日：2003-04-15
申请号：US09990261
申请日：2001-11-20
申请人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
发明人： Tsung-Hsuan Hsieh , Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G01R3126
CPC分类号： G01R27/2605
摘要： A circuit structure for measuring a capacitive load. The capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node. First, sources of the first and the second PMOS transistors and sources of the first and the second NMOS transistors are biased at a power source and a ground respectively. A non-synchronized voltage is applied to gates of the first and the second PMOS transistors and to gates of the first and the second NMOS transistors simultaneously. By grounding and floating the pad, a current flowing through the capacitive load is obtained to calculate the capacitance.
摘要翻译：用于测量电容性负载的电路结构。电容性负载耦合在第一和第二节点之间，并且第一PMOS和第一NMOS晶体管的漏极耦合到第一节点，并且第二PMOS和第二NMOS晶体管的漏极耦合到第二节点，并且垫连接到第二节点。首先，第一和第二PMOS晶体管的源极和第一和第二NMOS晶体管的源极分别偏置在电源和地。非同步电压同时施加到第一和第二PMOS晶体管的栅极和第一和第二NMOS晶体管的栅极。通过接地和浮动焊盘，获得流过电容性负载的电流来计算电容。

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