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    • 82. 发明授权
    • Live migration of a logical partition
    • 实时迁移逻辑分区
    • US07882326B2
    • 2011-02-01
    • US11690174
    • 2007-03-23
    • William Joseph ArmstrongDavid Anthony LarsonNaresh Nayar
    • William Joseph ArmstrongDavid Anthony LarsonNaresh Nayar
    • G06F12/00G06F21/00G06F13/00G06F13/28G06F9/455
    • G06F9/4856G06F9/45558G06F9/5077G06F2009/4557
    • A partition migration mechanism migrates a logical partition executing an operating system and resumes the logical partition before all resources in the logical partition have been migrated. When a partition is being migrated, a call checkpoint mechanism creates checkpoints of the state of the operating system when the partition manager is called. Before performing the call to the partition manager, a check is made to determine if all resources required by the call are available. If so, the partition manager call is executed. If all resources required by the call are not available, a resource fault is indicated, which causes the operating system state from the last checkpoint to be restored and a corresponding virtual CPU to be preempted until the resource that caused the fault becomes available. Exceptions that do not require the missing resource may be performed while the virtual CPU awaits the resource to become available.
    • 在迁移逻辑分区中的所有资源之前,分区迁移机制将迁移执行操作系统的逻辑分区并恢复逻辑分区。 当分区正在迁移时,调用检查点机制会在调用分区管理器时创建操作系统状态的检查点。 在执行对分区管理器的呼叫之前,进行检查以确定呼叫所需的所有资源是否可用。 如果是这样,则执行分区管理器调用。 如果呼叫所需的所有资源都不可用,则会指示资源故障,从而导致最后一个检查点的操作系统状态恢复,相应的虚拟CPU将被抢占,直到导致故障的资源变为可用。 可以在虚拟CPU等待资源变为可用时执行不需要缺少资源的异常。
    • 85. 发明授权
    • Method, apparatus, and product for an efficient virtualized time base in a scaleable multi-processor computer
    • 用于可扩展多处理器计算机中高效虚拟化时基的方法,设备和产品
    • US07512826B2
    • 2009-03-31
    • US11110180
    • 2005-04-20
    • William Joseph ArmstrongMichael J. CorriganNaresh NayarScott Barnett Swaney
    • William Joseph ArmstrongMichael J. CorriganNaresh NayarScott Barnett Swaney
    • G06F1/12
    • G06F1/14
    • A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.
    • 在用于在逻辑分区的数据处理系统中提供虚拟时基的数据处理系统中公开了一种方法,装置和计算机程序产品。 为多个处理器核心中的每一个确定时基。 时基用于指示当前时间到其中确定时基的一个处理器内核。 对于处理器核心,时基同步在一起,使得每个处理器核心包括其自己的同步时基副本。 对于其中一个处理器核心,生成与同步时基不同的虚拟时基,但与同步时基的至少一部分保持同步。 处理器核心利用虚拟时基而不是同步的时基来指示处理器核心的当前时间。 同步的时基和虚拟时基的一部分保持同步在一起。
    • 88. 发明申请
    • SELECTIVELY INVALIDATING ENTRIES IN AN ADDRESS TRANSLATION CACHE
    • 在地址翻译缓存中选择无效的入口
    • US20080168254A1
    • 2008-07-10
    • US12054538
    • 2008-03-25
    • Michael J. CorriganPaul LuVerne GodtlandJoaquin HinojosaCathy MayNaresh NayarEdward John Silha
    • Michael J. CorriganPaul LuVerne GodtlandJoaquin HinojosaCathy MayNaresh NayarEdward John Silha
    • G06F9/34
    • G06F12/1036G06F12/126G06F2212/1016G06F2212/683
    • An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.
    • 一种装置和方法选择性地使地址转换高速缓存中的条目无效,而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”,该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中,可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式,使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的,并且因此可以被保留,而其他条目无效。
    • 90. 发明申请
    • Apparatus and method for selectively invalidating entries in an address translation cache
    • 用于选择性地使地址转换高速缓存中的条目无效的装置和方法
    • US20070143565A1
    • 2007-06-21
    • US11304136
    • 2005-12-15
    • Michael CorriganPaul GodtlandJoaquin HinojosaCathy MayNaresh NayarEdward Silha
    • Michael CorriganPaul GodtlandJoaquin HinojosaCathy MayNaresh NayarEdward Silha
    • G06F12/00
    • G06F12/1036G06F12/126G06F2212/1016G06F2212/683
    • An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
    • 一种装置和方法选择性地使地址转换高速缓存中的条目无效,而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”,该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中,可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式,使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的,并且因此可以被保留,而地址转换高速缓存中的其他条目是无效的。