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81. 发明授权

US07259468B2 Structure of package 有权
标题翻译：包装结构
公开(公告)号：US07259468B2
公开(公告)日：2007-08-21
申请号：US10835571
申请日：2004-04-30
申请人： Wen-Kun Yang
发明人： Wen-Kun Yang
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/3114 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/02351 , H01L2224/05001 , H01L2224/05022 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.
摘要翻译：本发明公开了一种晶片级封装的结构。该结构包括第一图案化隔离层，导电层和第二图案化隔离层。第一图案化隔离层由IC（集成电路）的钝化层形成。导电层被配置为具有弯曲或绕组导电图案。第二图案化隔离层形成在导电层上方以具有多个开口，并且接触金属球可以形成在开口上以电耦合到印刷电路板。

82. 发明授权

US07196408B2 Fan out type wafer level package structure and method of the same 有权
标题翻译：扇出式晶圆级封装结构及其方法
公开(公告)号：US07196408B2
公开(公告)日：2007-03-27
申请号：US11301303
申请日：2005-12-12
申请人： Wen-Kun Yang , Wen-Pin Yang , Shih-Li Chen
发明人： Wen-Kun Yang , Wen-Pin Yang , Shih-Li Chen
IPC分类号： H01L23/02
CPC分类号： H01L21/561 , H01L23/3128 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/24195 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2224/82 , H01L2924/00
摘要： To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
摘要翻译：在新的基座上选择和放置标准模具，以获得模具之间适当和更宽的距离，而不是晶片上的模具的原始距离。包装结构具有比通过扇出型包装的模具尺寸更大的球阵列尺寸。此外，模具可以与被动部件或具有并排结构或堆叠结构的其它模具一起封装。

83. 发明授权

US06352868B1 Method and apparatus for wafer level burn-in 失效
标题翻译：晶圆级老化的方法和装置
公开(公告)号：US06352868B1
公开(公告)日：2002-03-05
申请号：US09524421
申请日：2000-03-11
申请人： Wen-Kun Yang
发明人： Wen-Kun Yang
IPC分类号： G01R3126
CPC分类号： G01R31/2879
摘要： A built-in circuit for wafer level burn-in of a die. The burn-in circuit includes a main burn-in control circuit, a word line control circuit and a bit line control circuit. A number of internal probing pads are also provided to receive voltages for stressing a gate oxide or capacitor oxide layer. A burn-in test system has a plurality of programmable power suppliers and programmable relays for providing control and power signals to a membrane or micro spring probe card used for the wafer level burn-in of multiple dice at the same time. Wafers are loaded and aligned in a prober with an automatic probing station and a hot chuck for the burn-in. The wafer level burn-in reduces the burn-in time of an integrated circuit chip from several days to several minutes.
摘要翻译：晶圆级老化的内置电路。老化电路包括主老化控制电路，字线控制电路和位线控制电路。还提供多个内部探测焊盘以接收用于施加栅极氧化物或电容器氧化物层的电压。老化测试系统具有多个可编程电源供应商和可编程继电器，用于同时向用于多个骰子的晶片级老化的膜或微型弹簧探针卡提供控制和功率信号。晶圆被装载并在探测器中与自动探测站和用于老化的热卡盘对准。晶圆级老化将集成电路芯片的老化时间从几天减少到几分钟。

84. 发明授权

US08232633B2 Image sensor package with dual substrates and the method of the same 有权
标题翻译：具有双基板的图像传感器封装及其相同的方法
公开(公告)号：US08232633B2
公开(公告)日：2012-07-31
申请号：US13289864
申请日：2011-11-04
申请人： Wen-Kun Yang
发明人： Wen-Kun Yang
IPC分类号： H01L23/48
CPC分类号： H01L27/14618 , H01L24/16 , H01L24/24 , H01L24/82 , H01L27/14625 , H01L2224/24225 , H01L2224/82039 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15788 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/351 , H01L2924/00
摘要： The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.
摘要翻译：具有双基板的图像传感器封装包括具有裸片接收开口的第一基板和穿过第一基板的多个第一通孔; 具有开口窗口的第二基板和穿过第二基板的多个第二通孔，形成在第一基板上。第二布线图案的一部分耦合到第三布线图案的一部分; 具有接收在所述管芯接收开口内的导电焊盘和感测阵列的图像裸片，并且所述感测阵列被所述裸片开口窗露出; 并且通孔导电材料被再填充到多个第二通孔中，多个第二通孔中的一些耦合到图像传感器的导电焊盘。

85. 发明授权

US07985626B2 Manufacturing tool for wafer level package and method of placing dies 有权
标题翻译：晶圆级封装的制造工具及放置模具的方法
公开(公告)号：US07985626B2
公开(公告)日：2011-07-26
申请号：US11158167
申请日：2005-06-20
申请人： Wen-Kun Yang , Wen-Pin Yang , Shih-li Chen
发明人： Wen-Kun Yang , Wen-Pin Yang , Shih-li Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/6835 , H01L21/67132 , H01L2221/68354 , H01L2924/0002 , Y10T29/53178 , Y10T29/53191 , Y10T29/53274 , Y10T428/28 , H01L2924/00
摘要： A manufacturing method of placing dice for a wafer level package comprises placing a plurality of dice on an elastic material, which is formed on a first base, and the elastic material of the present invention has viscosity in a first condition to adhere the plurality of dice; forming an adhesive material on a second base; adhering the plurality of dice on the adhesive material of the second base; and stripping the plurality of dice from the elastic material in a second condition.
摘要翻译：将用于晶片级封装的晶片的制造方法包括将多个晶片放置在形成在第一基底上的弹性材料上，并且本发明的弹性材料在第一条件下具有粘度以粘附多个骰子 ; 在第二基底上形成粘合剂材料; 将多个骰子粘附在第二基座的粘合材料上; 以及在第二状态下从所述弹性材料剥离所述多个骰子。

86. 发明申请

US20100301474A1 Semiconductor Device Package Structure and Method for the Same 有权
标题翻译：半导体器件封装结构及其方法
公开(公告)号：US20100301474A1
公开(公告)日：2010-12-02
申请号：US12855705
申请日：2010-08-13
申请人： Wen-Kun Yang
发明人： Wen-Kun Yang
IPC分类号： H01L23/52 , H01L21/50
CPC分类号： H01L23/49816 , H01L21/6835 , H01L23/5384 , H01L23/5389 , H01L23/544 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/31 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/105 , H01L25/16 , H01L2221/68354 , H01L2221/68359 , H01L2223/54426 , H01L2223/54473 , H01L2223/5448 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05624 , H01L2224/16225 , H01L2224/16235 , H01L2224/24225 , H01L2224/24227 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/83101 , H01L2224/83121 , H01L2224/8385 , H01L2224/92244 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2224/83 , H01L2924/00 , H01L2924/01022 , H01L2924/01028 , H01L2924/3512 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： The present invention discloses a semiconductor device package and the method for the same. The method includes preparing a first substrate and a second substrate; opening a die opening window through the second substrate by using laser or punching; preparing an adhesion material; attaching the first substrate to the second substrate by the adhesion material; aligning a die by using the aligning mark of the die metal pad and attaching the die onto the die metal pad with force by the adhesion material; forming a first dielectric layer on top surfaces of the second substrate and the die and pushing the first dielectric layer into gap between the side wall of the die and the side wall of the die opening window under vacuum condition; opening a plurality of via openings in the first dielectric layer; and forming a redistribution layer in the plurality of via openings and on the first dielectric layer.
摘要翻译：本发明公开了一种半导体器件封装及其制造方法。该方法包括制备第一衬底和第二衬底; 通过使用激光或冲孔打开通过第二基板的模具开口窗口; 制备粘合材料; 通过粘合材料将第一基板附着到第二基板; 通过使用模具金属垫的对准标记对准模具，并通过粘合材料的力将模具附着在模具金属垫上; 在所述第二基板和所述模具的顶表面上形成第一电介质层，并且在真空条件下将所述第一介电层推压到所述模具的侧壁与所述模具开口窗的侧壁之间的间隙中; 在所述第一电介质层中打开多个通孔; 以及在所述多个通孔中和所述第一介电层上形成再分配层。

87. 发明申请

US20100078655A1 Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same 有权
标题翻译：衬底结构，其内嵌有模具，并且在两个侧表面上具有双层叠层及其方法
公开(公告)号：US20100078655A1
公开(公告)日：2010-04-01
申请号：US12591812
申请日：2009-12-02
申请人： Wen-Kun Yang
发明人： Wen-Kun Yang
IPC分类号： H01L33/00 , H01L21/50 , H01L23/52
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/49816 , H01L23/5384 , H01L24/19 , H01L24/82 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05026 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05569 , H01L2224/12105 , H01L2224/13025 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82039 , H01L2224/92244 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/351 , H01L2924/3511 , H01L2924/3512 , H01L2924/00 , H01L2924/00014
摘要： The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is formed on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. During the formation, laser is introduced to cut the backside of the first substrate and an opening hole is formed in the first substrate to expose a part of the backside of the Au or Au/Ag metal layer of chip/die.
摘要翻译：本发明包括具有在模具金属焊盘上形成的管芯的第一衬底，形成在第一衬底的表面上的第一和第二布线电路。第二基板具有用于接收管芯的开口窗口，在第二基板的顶表面上形成第三布线电路，在第二基板的底表面上形成第四布线电路。将粘合剂材料填充到模具的背面和第一基板的顶表面之间以及模具的侧壁和模具的侧壁之间的间隙中，模具的通孔和第二基板的底侧。在形成期间，引入激光以切割第一基板的背面，并且在第一基板中形成开孔以暴露芯片/管芯的Au或Ag / Ag金属层的背面的一部分。

88. 发明申请

US20090096098A1 INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF THE SAME 审中-公开
公开(公告)号：US20090096098A1
公开(公告)日：2009-04-16
申请号：US11872164
申请日：2007-10-15
申请人： Wen-Kun Yang , Hsien-Wen Hsu
发明人： Wen-Kun Yang , Hsien-Wen Hsu
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L23/5389 , H01L24/19 , H01L2224/0401 , H01L2224/04105 , H01L2224/05571 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , H01L2924/00 , H01L2924/00012
摘要： The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers.

89. 发明授权

US07501310B2 Structure of image sensor module and method for manufacturing of wafer level package 有权
标题翻译：图像传感器模块的结构和晶圆级封装的制造方法
公开(公告)号：US07501310B2
公开(公告)日：2009-03-10
申请号：US11945723
申请日：2007-11-27
申请人： Wen-Kun Yang , Wen-Pin Yang
发明人： Wen-Kun Yang , Wen-Pin Yang
IPC分类号： H01L21/00
CPC分类号： H01L27/14687 , H01L21/561 , H01L24/97 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L31/0203 , H01L31/02325 , H01L2224/04105 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15788 , H05K1/189 , H01L2924/00 , H01L2224/83 , H01L2224/82
摘要： An image sensor die comprises a substrate and an image sensor array formed over the substrate. Micro lens are disposed on the image sensor array. A protection layer is formed on the micro lens to prevent the micro lens from particle containment.
摘要翻译：图像传感器管芯包括衬底和形成在衬底上的图像传感器阵列。微透镜设置在图像传感器阵列上。在微透镜上形成保护层，以防止微透镜受到颗粒的抑制。

90. 发明申请

US20090039532A1 SEMICONDUCTOR DEVICE PACKAGE HAVING A BACK SIDE PROTECTIVE SCHEME 审中-公开
标题翻译：具有背面保护方案的半导体器件封装
公开(公告)号：US20090039532A1
公开(公告)日：2009-02-12
申请号：US11835555
申请日：2007-08-08
申请人： Wen-Kun Yang , Hsien-Wen Hsu
发明人： Wen-Kun Yang , Hsien-Wen Hsu
IPC分类号： H01L23/52 , H01L21/00 , H01L23/48 , H01L29/40
CPC分类号： H01L23/3114 , H01L23/562 , H01L2924/0002 , H01L2924/01087 , H01L2924/00
摘要： The present invention provides a semiconductor device package, comprising a die having a back surface and an active surface formed thereon; an adhesive layer formed on the back surface of the die; a protection substrate formed on the adhesive layer; and a plurality of bumps formed on the active surface of the die for electrically connection. The present invention further provides a method for forming a semiconductor device package, comprising providing a plurality of die having a back surface and an active surface on a wafer; forming an adhesive layer on the back surface of the die; forming a protection substrates on the adhesive layer; forming a plurality of bumps on the active surface of each die; and dicing the plurality of die into individual die for singulation.
摘要翻译：本发明提供了一种半导体器件封装，其包括具有形成在其上的后表面和有源表面的管芯; 形成在模具的背面上的粘合剂层; 形成在粘合剂层上的保护基板; 以及形成在所述管芯的所述有源面上的电连接的多个凸点。本发明还提供了一种用于形成半导体器件封装的方法，包括在晶片上提供具有背面和活性表面的多个裸片; 在模具的后表面上形成粘合剂层; 在粘合剂层上形成保护基板; 在每个模具的活性表面上形成多个凸块; 并将多个管芯切割成单个管芯以进行切割。

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