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81. 发明授权

US06819003B2 Recessed encapsulated microelectronic devices and methods for formation 有权
标题翻译：嵌入式微电子器件和形成方法
公开(公告)号：US06819003B2
公开(公告)日：2004-11-16
申请号：US10320882
申请日：2002-12-16
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： H01L2328
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/85001 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic device package and method for manufacture. In one embodiment, the device package can include a support member having a first surface, a second surface facing opposite the first surface and a cavity extending through the support member from the first surface to the second surface. A microelectronic device is disposed in the cavity and is supported in the cavity with a removable retention member. The microelectronic device is electrically coupled to the support member and is partially surrounded with an encapsulating material. The removable retention member is then removed to expose a surface of the microelectronic device. Accordingly, the package can have a low profile because the encapsulating material does not surround one of the microelectronic device surfaces. In one embodiment, a heat conductive material can be engaged with the exposed surface of the microelectronic device to increase the rate at which heat is transferred away from the microelectronic device.
摘要翻译：一种微电子器件封装及其制造方法。在一个实施例中，装置包装可以包括具有第一表面，与第一表面相对的第二表面的支撑构件和从第一表面延伸穿过支撑构件到第二表面的空腔。微电子器件设置在空腔中并且用可移除的保持构件支撑在空腔中。微电子器件电耦合到支撑构件并且被封装材料部分地包围。然后去除可移除的保持构件以暴露微电子器件的表面。因此，由于封装材料不包围微电子器件表面之一，所以封装可以具有低的外形。在一个实施例中，导热材料可以与微电子器件的暴露表面接合以增加热量从微电子器件转移的速率。

82. 发明授权

US06814778B1 Method for continuous mode solder jet apparatus 失效
标题翻译：连续式焊料喷射装置的方法
公开(公告)号：US06814778B1
公开(公告)日：2004-11-09
申请号：US09435455
申请日：1999-11-05
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： B05D106
CPC分类号： H01L21/6715 , B23K3/0623 , B41J2/09 , H01L21/67144 , H05K3/3457 , H05K2203/105 , H05K2203/163
摘要： A solder jet apparatus is disclosed The solder jet apparatus is a continuous mode solder jet that includes a blanking system and raster scan system. The use of the raster scan and blanking systems allows for a continuous stream of solder to be placed anywhere on the surface in any desired X-Y plane. This allows for greater accuracy as well as greater product throughput. Additionally, with the raster scan system, repairs to existing soldered surfaces can be quickly and easily performed using a map of the defects for directing the solder to the defects.
摘要翻译：公开了一种焊料喷射装置。焊料喷射装置是包括消隐系统和光栅扫描系统的连续模式焊料喷射。光栅扫描和消隐系统的使用允许将连续的焊料流放置在任何所需的X-Y平面上的任何地方。这允许更高的精度以及更大的产品吞吐量。另外，使用光栅扫描系统，可以使用用于将焊料引导到缺陷的缺陷图快速轻松地进行现有焊接表面的修复。

83. 发明授权

US06808947B2 Substrate mapping 失效
标题翻译：基板映射
公开(公告)号：US06808947B2
公开(公告)日：2004-10-26
申请号：US10423127
申请日：2003-04-25
申请人： Warren M. Farnworth , Derek J. Gochnour
发明人： Warren M. Farnworth , Derek J. Gochnour
IPC分类号： H01L2166
CPC分类号： H01L23/544 , H01L24/83 , H01L2223/54413 , H01L2223/5442 , H01L2223/54473 , H01L2223/54486 , H01L2224/83192 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , Y10T29/49004 , Y10T29/49146 , Y10T29/53043 , Y10T29/53178 , Y10T29/53187 , H01L2924/00
摘要： A method for fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die is attached to the die attach sites in accord with the information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
摘要翻译：一种制造半导体管芯封装的方法，包括安装基板和附接到其上的裸片。安装基板包括多个管芯附接位置和具有衬底识别信息的指示符。芯片附着位点被评估并分类为良好或有缺陷的裸片附着位点，其中所评估的信息作为映射信息保存在电子文件中。根据信息将模具附接到管芯附着位置，其中已知的好的裸片附接到良好的裸片附着位置，并且已知的有缺陷的裸片附着到有缺陷的芯片附着位置。然后将组件封装在传递模制操作中。

84. 发明授权

US06801048B2 Device and method for testing integrated circuit dice in an integrated circuit module 失效
标题翻译：在集成电路模块中测试集成电路芯片的装置和方法
公开(公告)号：US06801048B2
公开(公告)日：2004-10-05
申请号：US10396163
申请日：2003-03-25
申请人： Warren M. Farnworth , James M. Wark , Eric S. Nelson , Kevin G. Duesman
发明人： Warren M. Farnworth , James M. Wark , Eric S. Nelson , Kevin G. Duesman
IPC分类号： G01R3128
CPC分类号： G11C29/785 , G01R31/2884 , G01R31/31701 , G01R31/31719 , G01R31/318513 , G11C29/1201 , G11C29/46 , G11C29/80 , G11C29/808 , H01L22/22 , H01L2224/48091 , H01L2224/48227 , H04J2203/0062 , H01L2924/00014
摘要： An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements' addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.
摘要翻译：诸如多芯片模块（MCM）的IC模块包括多个IC芯片，每个具有测试模式使能焊盘，例如输出使能焊盘。集成到MCM基板中的保险丝将每个管芯的测试模式使能接合焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的一个接地针脚。通过向测试模式施加电源电压，使焊盘通过N / C引脚，在骰子中启动测试模式。一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的接地电压使得接合焊盘通过接地引脚，使得电阻器禁用骰子中的测试模式并启动操作模式。因此，封装在IC模块中的裸片可以在封装后进行测试。一旦测试模式已经启动并且用于修复在测试期间发现的任何故障元件，执行这种测试的方法包括向骰子提供测试信号，从骰子接收响应信号，评估响应信号以识别骰子中的任何故障元件，使用编程电压将故障元件的地址编程为骰子中的防熔丝，确认通过确定防熔丝的电阻，重新测试骰子，从重新测试的骰子接收响应信号来编程地址，并评估响应信号以确认所有维修。

85. 发明授权

US06797545B2 Method and apparatus for fabricating electronic device 失效
标题翻译：用于制造电子设备的方法和装置
公开(公告)号：US06797545B2
公开(公告)日：2004-09-28
申请号：US10259510
申请日：2002-09-30
申请人： Warren M. Farnworth , Kevin G. Duesman , Alan G. Wood
发明人： Warren M. Farnworth , Kevin G. Duesman , Alan G. Wood
IPC分类号： H10L2182
CPC分类号： G11C29/88 , G11C5/063 , G11C29/006 , H01L22/22 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.
摘要翻译：形成在相邻制造的电子设备之间的街道区域中的逻辑电路可以用作辅助或冗余组件来挽救一个或多个否则有缺陷的设备。逻辑电路选择性地耦合到有缺陷的装置，以直接替换或促进在一个或多个制造的装置上更换有缺陷的部件，由此导致单个可操作的电子装置。本发明可以用于增加电子设备，特别是半导体集成电路的生产成本。本发明允许在半导体层的正常金属化期间制造任意布线，以在形成设备的正常布线/电路的同时互连电子器件。

86. 发明授权

US06794699B2 Annular gate and technique for fabricating an annular gate 有权
标题翻译：环形门和制造环形门的技术
公开(公告)号：US06794699B2
公开(公告)日：2004-09-21
申请号：US10230568
申请日：2002-08-29
申请人： Lucien J. Bissey , Kevin G. Duesman , Warren M. Farnworth
发明人： Lucien J. Bissey , Kevin G. Duesman , Warren M. Farnworth
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/4238 , H01L29/66666 , H01L29/7827
摘要： A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
摘要翻译：具有具有环形栅极区域的垂直取向的存取晶体管的存储器结构和用于制造该结构的方法。更具体地，制造晶体管，使得晶体管的沟道相对于衬底的表面向外延伸。围绕垂直通道制造环形门，使得其部分地或完全地围绕通道。还可以实现埋置的环形位线。在用环形栅极制造垂直取向的晶体管之后，可以在晶体管上制造存储器件以提供存储器单元。

87. 发明授权

US06773957B2 Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures 有权
标题翻译：用于制造用于半导体器件和所得结构的间隔物的立体光刻方法和装置
公开(公告)号：US06773957B2
公开(公告)日：2004-08-10
申请号：US10246318
申请日：2002-09-17
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2144
CPC分类号： H01L24/81 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G03F7/70416 , H01L24/14 , H01L24/75 , H01L2224/05568 , H01L2224/05573 , H01L2224/10135 , H01L2224/13099 , H01L2224/14 , H01L2224/75 , H01L2224/81136 , H01L2224/81139 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/351 , H05K1/0269 , H05K3/0023 , H05K3/303 , H05K2201/09909 , H05K2201/10568 , H05K2201/10674 , H05K2201/10734 , H05K2201/2036 , Y02P70/613 , H01L2924/00 , H01L2224/05599
摘要： Insulative spacers to be disposed on a surface of a semiconductor device component and methods of fabricating and placing the insulative spacers on semiconductor device components. Upon assembly of the semiconductor device component face-down upon a higher level substrate and establishing electrical communication between the semiconductor device component and the higher level substrate, the insulative spacers define a minimum, substantially uniform distance between the semiconductor device component and the higher level substrate. The insulative spacers also prevent tilting or tipping of the semiconductor device component relative to the higher level substrate. The insulative spacers may be preformed or fabricated on a surface of the semiconductor device component. A stereolithographic method for fabricating the insulative spacers is disclosed, which may employ a machine vision system to recognize the position and orientation of a substrate to which material is to be applied and control fabrication based upon the recognized position and orientation.
摘要翻译：要设置在半导体器件部件的表面上的绝缘间隔物以及在半导体器件部件上制造和放置绝缘间隔物的方法。半导体器件组件在较高级别的衬底上面朝下组装并建立半导体器件部件和较高级衬底之间的电连通时，绝缘衬垫限定了半导体器件部件和较高级衬底之间的最小，基本均匀的距离。绝缘间隔物还防止半导体器件部件相对于较高级衬底的倾斜或倾斜。可以在半导体器件部件的表面上预制或制造绝缘间隔物。公开了用于制造绝缘间隔物的立体光刻方法，其可以使用机器视觉系统来识别要施加材料的基底的位置和取向，并且基于识别的位置和取向来控制制造。

88. 发明授权

US06740960B1 Semiconductor package including flex circuit, interconnects and dense array external contacts 有权
标题翻译：半导体封装包括柔性电路，互连和密集阵列外部触点
公开(公告)号：US06740960B1
公开(公告)日：2004-05-25
申请号：US10231752
申请日：2002-08-29
申请人： Warren M. Farnworth , Alan G. Wood , Mike Brooks
发明人： Warren M. Farnworth , Alan G. Wood , Mike Brooks
IPC分类号： H01L23495
CPC分类号： H01L23/49827 , H01L23/4985 , H01L24/45 , H01L24/48 , H01L2224/02333 , H01L2224/451 , H01L2224/48091 , H01L2224/4813 , H01L2224/48465 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in electrical communication with the external contacts. The package also includes interconnects configured to provide separate electrical paths between die contacts (e.g., bond pads), and the conductors on the flex circuit. Several different embodiments of interconnects are provided including: bumps on the die contacts, bonded to the flex circuit conductors with a conductive adhesive layer; polymer bumps on the conductors, or die contacts, applied in a semi-cured state and then fully cured; solder bumps on the die contacts and conductors, bonded to one another using a bonding tool; rivet-like bonded connections between the conductors and die contacts, formed using metal bumps and a wire bonding or ball bonding apparatus; single point bonded connections between the conductors and die contacts, formed with a bonding tool; and wire bonds between the conductors and die contacts.
摘要翻译：提供了一种芯片级半导体封装和一种制造该封装的方法。该封装包括半导体管芯和连接到管芯的表面的柔性电路。柔性电路包括具有密集阵列的外部触点的聚合物基板和与外部触点电连通的导体图案。封装还包括被配置为在管芯触头（例如，焊盘）之间提供分开的电路径的互连件以及柔性电路上的导体。提供了互连的几个不同实施例，包括：在裸片上的凸起接触，用导电粘合剂层粘合到柔性电路导体上; 导体上的聚合物凸块或模具接触件以半固化状态施加，然后完全固化; 使用焊接工具彼此接合的管芯触点和导体上的焊料凸块; 使用金属凸块和引线接合或球焊接装置形成的导体和裸片接触之间的铆钉状接合连接; 导体和裸片接点之间的单点接合连接，用接合工具形成; 以及导体和裸片接触之间的引线键合。

89. 发明授权

US06740476B2 Surface smoothing of stereolithographically formed 3-D objects 失效
标题翻译：立体光刻形成的三维物体的表面平滑
公开(公告)号：US06740476B2
公开(公告)日：2004-05-25
申请号：US10230897
申请日：2002-08-29
申请人： Warren M. Farnworth , Kevin G. Duesman
发明人： Warren M. Farnworth , Kevin G. Duesman
IPC分类号： G03F726
CPC分类号： G03F7/0037 , B29C37/005 , B29C41/48 , B29C64/40 , B29C73/00 , B29C2035/0827 , B29C2035/0838 , B29K2995/0073 , B33Y10/00 , B33Y30/00 , Y10S430/146
摘要： A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin layer of liquid photopolymer on a prior layer. Crevices formed at the layer interfaces are filled by a stereolithographic method comprising lifting the multilayered structure from the liquid photopolymer, draining excess liquid therefrom, tilting the structure to provide an acute angle of incidence between an incident radiation beam and a side wall of the object, and applying radiation to the crevice to polymerize at least the surface of a quantity of liquid photopolymer therein. The structure may then be subjected to a separate final full cure to fully harden the structure. An exemplary use is the packaging of electronic components and the like.
摘要翻译：一种用于形成包含多个上层的聚合物结构的立体光刻方法和装置，每个层通过在先前层上聚合薄层的液体光聚合物而形成。在层界面处形成的裂缝由立体光刻法填充，其包括从液体光聚合物提起多层结构，从其中排出多余的液体，使结构倾斜以提供入射辐射束与物体的侧壁之间的锐角入射角，并向所述缝隙施加辐射以至少使其中的液体光聚合物的表面聚合。然后可以对该结构进行单独的最终完全固化以使结构完全硬化。示例性的用途是电子部件等的包装。

90. 发明授权

US06713788B2 Opto-electric mounting apparatus 失效
标题翻译：光电安装装置
公开(公告)号：US06713788B2
公开(公告)日：2004-03-30
申请号：US10341451
申请日：2003-01-14
申请人： Kevin G. Duesman , Warren M. Farnworth
发明人： Kevin G. Duesman , Warren M. Farnworth
IPC分类号： H01L3300
CPC分类号： H05K1/181 , H01L25/167 , H01L2924/0002 , H01L2924/3011 , H05K2201/10121 , H05K2201/10515 , Y02P70/611 , H01L2924/00
摘要： An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, an opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned. Also disclosed is a substrate-mounted optical transmission system that may be used in connection with the opto-electric device.
摘要翻译：集成电路设置有一个或多个连接器，其允许光电装置直接安装在集成电路的顶部或其下方。可以在集成电路上定义多个光电器件接口区域，使得光电器件可以在多个方向上连接，或者可以连接多个光电器件。此外，可以提供光电装置接口，其使得光电装置的导线以尽可能短的距离被引导到相应的集成电路引线，而不管光电装置如何定位。还公开了可以与光电装置结合使用的基板安装的光传输系统。

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