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81. 外观设计

USD338541S Roof tile 失效
公开(公告)号：USD338541S
公开(公告)日：1993-08-17
申请号：US704638
申请日：1991-05-23
申请人： John A. Fifield
设计人： John A. Fifield

82. 发明授权

US5070671A Roof tiles 失效
标题翻译：屋顶
公开(公告)号：US5070671A
公开(公告)日：1991-12-10
申请号：US536591
申请日：1990-06-28
申请人： John A. Fifield , Leslie G. Hammond
发明人： John A. Fifield , Leslie G. Hammond
IPC分类号： E04D1/04 , E04D1/16
CPC分类号： E04D1/04 , E04D1/16
摘要： An interlocking roof tile (1) of which the leading end portion (12) at least as far as the lower end of, and including the underlock (6) is tapered in the direction of the leading edge (5) of the tile (1).
摘要翻译： PCT No.PCT / GB89 / 00044 Sec。 371日期1990年6月28日第 102（e）日期1990年6月28日PCT 1989年1月17日PCT PCT。出版物WO89 / 06728 日期：1989年7月27日。一种互锁屋顶瓦（1），其前端部分（12）至少在下端并且包括锁定件（6）的前端部分（12）沿着前缘 5）。

83. 发明授权

US5022006A Semiconductor memory having bit lines with isolation circuits connected between redundant and normal memory cells 失效
标题翻译：半导体存储器，具有连接在冗余和正常存储单元之间的隔离电路的位线
公开(公告)号：US5022006A
公开(公告)日：1991-06-04
申请号：US175883
申请日：1988-04-01
申请人： John A. Fifield , Steven W. Tomashot
发明人： John A. Fifield , Steven W. Tomashot
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04
CPC分类号： G11C29/84
摘要： A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available each of a plurality of sub-arrays of normal memory.

84. 发明授权

US4459609A Charge-stabilized memory 失效
标题翻译：电荷稳定记忆
公开(公告)号：US4459609A
公开(公告)日：1984-07-10
申请号：US301563
申请日：1981-09-14
申请人： John A. Fifield , Lawrence G. Heller , Lloyd A. Walls
发明人： John A. Fifield , Lawrence G. Heller , Lloyd A. Walls
IPC分类号： G11C11/404 , G11C11/56 , G11C27/02 , H01L29/78 , G11C11/24 , H01L27/02
CPC分类号： G11C11/404 , G11C11/565 , G11C27/024 , Y10S257/92
摘要： A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.
摘要翻译：提供了一种密集存储器，其包括使用电荷填充和溢出技术的一个器件随机存取存储器单元，其中存储节点下方的势阱填充有电荷，并且超过预定水平的超量电荷溢出到连接到通过由字线上的脉冲控制的通道区域的感测线。信息的一位或两位或更多位可以在任何给定的时刻存储在潜在井中。取决于施加到存储节点或电极的电压增量的值，给定的模拟电荷包被存储在形成在存储电极下方的势阱中。通过向字线施加电压来读取信息以打开通道区域，然后以分数，优选为一半的增量降低存储电极上的电压。通过连接到感测线的感测电路来检测从存储电极下方的电位阱溢出的电荷分组的充电。为了将信息重写到势阱中，电压的原始增量被施加到存储节点，并且感测线被拉到地，使得扩散区充当势阱的电荷源。

85. 发明授权

US08773920B2 Reference generator with programmable M and B parameters and methods of use 有权
标题翻译：具有可编程M和B参数的参考发生器和使用方法
公开(公告)号：US08773920B2
公开(公告)日：2014-07-08
申请号：US13401368
申请日：2012-02-21
申请人： Darren L. Anand , John A. Fifield
发明人： Darren L. Anand , John A. Fifield
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , Y10T307/718
摘要： A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.
摘要翻译：提供了具有可编程m和b参数和使用方法的参考发生器。电路包括可操作以产生包括电源电压的一部分的第一电压的第一发生器。电路还包括可操作以产生第二电压的第二发生器。该电路还包括可操作以输出包括第一和第二电压之和的参考电压的混频器和缓冲电路。

86. 发明申请

US20120178239A1 PROGRAMMABLE SEMICONDUCTOR DEVICE 有权
标题翻译：可编程半导体器件
公开(公告)号：US20120178239A1
公开(公告)日：2012-07-12
申请号：US13427162
申请日：2012-03-22
申请人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
发明人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
IPC分类号： H01L21/768
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译：可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

87. 发明授权

US08189419B2 Apparatus for nonvolatile multi-programmable electronic fuse system 有权
标题翻译：非易失性多可编程电子保险丝系统的装置
公开(公告)号：US08189419B2
公开(公告)日：2012-05-29
申请号：US12498175
申请日：2009-07-06
申请人： Howard H. Chen , John A. Fifield , Louis C. Hsu
发明人： Howard H. Chen , John A. Fifield , Louis C. Hsu
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/16
摘要： Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.
摘要翻译：提供具有多重重新编程能力的电子保险丝（e-fuse）系统。在一个方面，提供了一种可再编程电子熔丝系统，其包括第一电熔丝串; 第二个电熔丝串; 连接到第一电熔丝串和第二电熔丝串的选择器，被配置为交替地从要编程的第一电熔丝串或第二电熔丝串中选择电熔丝; 以及连接到第一电熔丝串和第二电熔丝串两者的比较器，被配置为将第一电熔丝串两端的电压与第二电熔丝串的电压进行比较，以确定电子熔丝串的编程状态，保险丝系统

88. 发明申请

US20120075918A1 SRAM Having Wordline Up-Level Voltage Adjustable to Assist Bitcell Stability and Design Structure for Same 有权
标题翻译： SRAM具有可调节字节上位电压以协助位单元稳定性和设计结构
公开(公告)号：US20120075918A1
公开(公告)日：2012-03-29
申请号：US12892160
申请日：2010-09-28
申请人： Igor Arsovski , John A. Fifield , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , John A. Fifield , Robert M. Houle , Harold Pilo
IPC分类号： G11C11/00 , G11C8/08 , G06F17/50
CPC分类号： G11C8/08 , G11C11/413
摘要： An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.
摘要翻译：一种集成电路，包括含有字线的存储器和具有SRAM存储元件并连接到字线的位单元。提供了字线上级辅助电路，其设计和配置为提供多个可选择的电压值，其可被选择以提供在存储器读周期和/或写周期期间提供给位单元的字线上电压。在一个示例中，所选择的电压值基于所制造的比特单元的表征来选择，以便降低位单元经历稳定性故障的可能性。

89. 发明申请

US20110032025A1 PROGRAMMABLE SEMICONDUCTOR DEVICE 有权
标题翻译：可编程半导体器件
公开(公告)号：US20110032025A1
公开(公告)日：2011-02-10
申请号：US12911379
申请日：2010-10-25
申请人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
发明人： William R. Tonti , Wayne S. Berry , John A. Fifield , William H. Guthrie , Richard S. Kontra
IPC分类号： H01H37/76 , H01L21/768
CPC分类号： G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
摘要翻译：可编程器件包括衬底（10）; 绝缘体（13）; 绝缘体上的细长半导体材料（12），具有第一和第二端的细长半导体材料和上表面S; 第一端部（12a）比第二端部（12b）大得多，金属材料设置在上表面上; 所述金属材料可响应于流过半导体材料和金属材料的电流I而沿着上表面物理迁移。

90. 发明授权

US07733161B2 Voltage boost system, IC and design structure 失效
标题翻译：电压升压系统，集成电路和设计结构
公开(公告)号：US07733161B2
公开(公告)日：2010-06-08
申请号：US12031729
申请日：2008-02-15
申请人： Jeffrey H. Dreibelbis , John A. Fifield
发明人： Jeffrey H. Dreibelbis , John A. Fifield
IPC分类号： H02M3/18 , G05F3/16
CPC分类号： H02M3/07
摘要： A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used.
摘要翻译：公开了升压系统，IC和设计结构，用于提高电源电压，同时防止n阱结构的向前偏置。升压系统可以包括使用至少一个升压子电路产生第一升压电压的第一升压电路，所述至少一个升压子电路中的每一个在n阱中具有输出通路; 产生第二升压电压的第二升压电路，使用第二升压电压对每个输出通道的n阱进行偏置，其中第二升压电压大于第一升压电压。电压升压子电路可以使用栅极控制电路来减小栅极氧化物应力，从而允许使用较低电压电平的FET。

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