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81. 发明申请

US20050245039A1 PCMO thin film with resistance random access memory (RRAM) characteristics 有权
标题翻译：具有电阻随机存取存储器（RRAM）特性的PCMO薄膜
公开(公告)号：US20050245039A1
公开(公告)日：2005-11-03
申请号：US10836689
申请日：2004-04-30
申请人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： C01G45/00 , C01F11/02 , C01F17/00 , C01G99/00 , G11C13/00 , H01L21/00 , H01L21/20 , H01L27/10 , H01L43/08 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1
摘要翻译：已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜组成，其中0.1 _0.78Mn^{4+</SUP>_0.22O^2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

82. 发明授权

US07531466B2 Metal organic deposition precursor solution synthesis and terbium-doped SiO2 thin film deposition 失效
标题翻译：金属有机沉积前驱体溶液合成和铽掺杂SiO2薄膜沉积
公开(公告)号：US07531466B2
公开(公告)日：2009-05-12
申请号：US11494141
申请日：2006-07-26
申请人： Wei-Wei Zhuang , Yoshi Ono , Tingkai Li
发明人： Wei-Wei Zhuang , Yoshi Ono , Tingkai Li
IPC分类号： H01L21/31
CPC分类号： C23C18/1295 , C23C18/1208 , C23C18/1279 , C23C18/1283
摘要： A method of making a doped silicon oxide thin film using a doped silicon oxide precursor solution includes mixing a silicon source in an organic acid and adding 2-methoxyethyl ether to the silicon source and organic acid to from a preliminary precursor solution. The resultant solution is heated, stirred and filtered. A doping impurity is dissolved in 2-methoxyethanol to from a doped source solution, and the resultant solution mixed with the previously described resultant solution to from a doped silicon oxide precursor solution. A doped silicon oxide thin film if formed on a wafer by spin coating. The thin film and the wafer are baked at progressively increasing temperatures and the thin film and the wafer are annealed.
摘要翻译：使用掺杂的氧化硅前体溶液制造掺杂的氧化硅薄膜的方法包括将有机酸中的硅源混合并向硅源和有机酸中加入2-甲氧基乙醚至初始前体溶液。将所得溶液加热，搅拌并过滤。将掺杂杂质从掺杂的源溶液中溶解在2-甲氧基乙醇中，并将所得溶液与先前所述的溶液混合从掺杂的氧化硅前体溶液中。如果通过旋涂在晶片上形成掺杂的氧化硅薄膜。在逐渐升高的温度下烘烤薄膜和晶片，并对薄膜和晶片进行退火。

83. 发明申请

US20070221975A1 Bipolar switching PCMO capacitor 有权
标题翻译：双极开关PCMO电容
公开(公告)号：US20070221975A1
公开(公告)日：2007-09-27
申请号：US11805177
申请日：2007-05-22
申请人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： H01L29/92
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616
摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.
摘要翻译：提供了多层Pr 1 x 1 x x MnO 3（PCMO）薄膜电容器和相关的沉积方法，用于形成双极开关薄膜。该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶的PCMO层; 形成具有双极开关特性的多层PCMO膜; 并形成覆盖PCMO膜的顶部电极。如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

84. 发明申请

US20060214172A1 Electroluminescence device with nanotip diodes 有权
标题翻译：具有纳米二极管的电致发光器件
公开(公告)号：US20060214172A1
公开(公告)日：2006-09-28
申请号：US11090386
申请日：2005-03-23
申请人： Sheng Hsu , Tingkai Li , Wei-Wei Zhuang
发明人： Sheng Hsu , Tingkai Li , Wei-Wei Zhuang
IPC分类号： H01L33/00 , H01L21/00
CPC分类号： H01L33/08 , B82Y20/00 , H01L33/18 , H01L33/24 , H01L33/34 , H01L33/502 , Y10S977/834
摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.
摘要翻译：提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

85. 发明申请

US20050207265A1 Memory cell with an asymmetric crystalline structure 有权
标题翻译：具有不对称晶体结构的记忆单元
公开(公告)号：US20050207265A1
公开(公告)日：2005-09-22
申请号：US11130983
申请日：2005-05-16
申请人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
发明人： Sheng Hsu , Tingkai Li , David Evans , Wei-Wei Zhuang , Wei Pan
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L45/00 , G11C8/02
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1625
摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
摘要翻译：提供了非对称结构的存储单元和制造方法。该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度的第一层。在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

86. 发明申请

US20050037520A1 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
标题翻译：当与高度结晶的种子层集成时，获得PCMO薄膜上的可逆电阻开关的方法
公开(公告)号：US20050037520A1
公开(公告)日：2005-02-17
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David Evans , Sheng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.
摘要翻译：当与高度结晶的种子层集成时，用于获得PCMO薄膜上的可逆电阻开关的方法包括通过MOCVD沉积高度结晶形式的PCMO的种子层，薄膜的厚度为约50埃至300埃通过旋转涂覆沉积种子层上的第二PCMO薄膜层，其厚度为约500埃至3000埃以形成组合的PCMO层; 通过施加约-4V至-5V之间的脉冲宽度在约75ns至1个音箱之间的负电脉冲来增加半导体器件中组合的PCMO膜的电阻; 并且通过施加脉冲宽度大于2.0个音箱的约+ 2.5V至+ 4V之间的正电脉冲来降低半导体器件中组合的PCMO层的电阻。

87. 发明申请

US20070284575A1 Metal/semiconductor/metal current limiter 有权
标题翻译：金属/半导体/金属限流器
公开(公告)号：US20070284575A1
公开(公告)日：2007-12-13
申请号：US11893402
申请日：2007-08-15
申请人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
发明人： Tingkai Li , Sheng Hsu , Wei-Wei Zhuang , David Evans
IPC分类号： H01L29/12
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) current limiter and resistance memory cell with an MSM current limiter. The method comprises: providing a substrate; forming an MSM bottom electrode overlying the substrate; forming a ZnOx semiconductor layer overlying the MSM bottom electrode, where x is in the range between about 1 and about 2, inclusive; and, forming an MSM top electrode overlying the semiconductor layer. The ZnOx semiconductor can be formed through a number of different processes such as spin-coating, direct current (DC) sputtering, radio frequency (RF) sputtering, metalorganic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).
摘要翻译：提供了一种用于形成具有MSM限流器的金属/半导体/金属（MSM）限流器和电阻存储器单元的方法。该方法包括：提供衬底; 形成覆盖所述衬底的MSM底部电极; 形成覆盖MSM底部电极的ZnO x半导体层，其中x在约1和约2之间的范围内; 并且形成覆盖半导体层的MSM顶部电极。可以通过旋涂，直流（DC）溅射，射频（RF）溅射，金属有机化学气相沉积（MOCVD）或原子层沉积（ALD）等多种不同的工艺形成ZnO x半导体。

88. 发明申请

US20060194403A1 PCMO thin film with controlled resistance characteristics 审中-公开
标题翻译： PCMO薄膜具有受控电阻特性
公开(公告)号：US20060194403A1
公开(公告)日：2006-08-31
申请号：US11378719
申请日：2006-03-17
申请人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： H01L21/20
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1
摘要翻译：已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜组成，其中0.1 _0.78Mn^{4+</SUP>_0.22O^2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

89. 发明申请

US20060068099A1 Grading PrxCa1-xMnO3 thin films by metalorganic chemical vapor deposition 审中-公开
标题翻译：通过金属有机化学气相沉积法分级PrxCa1-xMnO3薄膜
公开(公告)号：US20060068099A1
公开(公告)日：2006-03-30
申请号：US10957304
申请日：2004-09-30
申请人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： C23C16/00
CPC分类号： C23C16/40 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616
摘要： The present invention discloses a method to achieve grading PCMO thin film for use in RRAM memory devices since the contents of Ca, Mn and Pr in a PCMO film can have great influence on its switching property. By choosing precursors for Pr, Ca and Mn having different deposition rate behaviors with respect to deposition temperature or vaporizer temperature, PCMO thin film of grading Pr, Ca or Mn distribution can be achieved by varying that process condition during deposition. The present invention can also be broadly applied to the fabrication of any multicomponent grading thin film process by varying any of the deposition parameters after preparing multiple precursors to have different deposition rate behaviors with respect to that particular process parameter. The present invention starts with a proper selection of precursors in which the selected precursors have different deposition rates with respect to at least one deposition condition such as deposition temperature or vaporizer temperature. The precursors can then be arranged in different delivery systems, or can be pre-mixed in a proper ratio for use in a delivery system, or in any other combinations such as a mixture of two or three liquid precursors using a direct liquid injection and a separate gaseous precursor delivery system for gaseous process gas. Then by varying the appropriate deposition condition, a grading thin film can be achieved.
摘要翻译：本发明公开了一种用于RRAM存储器件中的PCMO薄膜分级的方法，因为PCMO薄膜中Ca，Mn和Pr的含量对其开关性能有很大的影响。通过选择相对于沉积温度或蒸发器温度具有不同沉积速率行为的Pr，Ca和Mn的前体，可以通过在沉积期间改变该工艺条件来实现分级Pr，Ca或Mn分布的PCMO薄膜。本发明还可以广泛地应用于任何多组分分级薄膜工艺的制造，其通过在制备多种前体之后改变任何沉积参数以相对于该特定工艺参数具有不同的沉积速率行为。本发明开始于适当选择前体，其中所选择的前体相对于至少一个沉积条件例如沉积温度或蒸发器温度具有不同的沉积速率。然后可将前体布置在不同的递送系统中，或者可以以适当的比例预先混合以用于递送系统，或者以任何其它组合例如使用直接液体注射的两种或三种液体前体的混合物用于气态工艺气体的单独的气态前体输送系统。然后通过改变适当的沉积条件，可以实现分级薄膜。

90. 发明申请

US20050266686A1 Method of substrate surface treatment for RRAM thin film deposition 有权
标题翻译： RRAM薄膜沉积的基板表面处理方法
公开(公告)号：US20050266686A1
公开(公告)日：2005-12-01
申请号：US10855088
申请日：2004-05-27
申请人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David Evans , Sheng Hsu
发明人： Wei-Wei Zhuang , Tingkai Li , Wei Pan , David Evans , Sheng Hsu
IPC分类号： C23C18/12 , C30B23/02 , C30B29/24 , H01L21/44 , H01L45/00
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1241 , C23C18/1283 , C30B23/02 , C30B29/24 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1608
摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.
摘要翻译：制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

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