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81. 发明授权

US08120937B2 Ternary content addressable memory using phase change devices 有权
标题翻译：使用相变装置的三元内容可寻址存储器
公开(公告)号：US08120937B2
公开(公告)日：2012-02-21
申请号：US12399346
申请日：2009-03-06
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C10/00 , G11C11/00 , G11C11/56
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

82. 发明授权

US08116126B2 Measurement method for reading multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 失效
标题翻译：使用测量时间延迟读取多级存储单元作为电平定义的特征参数的测量方法
公开(公告)号：US08116126B2
公开(公告)日：2012-02-14
申请号：US12542146
申请日：2009-08-17
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A memory system includes a memory cell configured to represent at least two binary values, a bit line coupled to the memory cell, and first and second comparators coupled to the bit line that, respectively, compare a first and second reference value to a value of a parameter of the bit-line. The system also includes a first and second timers configured to measures a time for the parameter of the bit line to decay. The system also includes a logic unit coupled to the first and second timers that selects the time for the parameter of the bit line to decay from to a first value or a second value.
摘要翻译：存储器系统包括被配置为表示至少两个二进制值的存储器单元，耦合到存储单元的位线，以及耦合到位线的第一和第二比较器，其分别将第一和第二参考值与位线的参数。该系统还包括配置成测量位线参数衰减的时间的第一和第二定时器。该系统还包括耦合到第一和第二定时器的逻辑单元，其选择位线的参数从第一值或第二值衰减的时间。

83. 发明授权

US08107276B2 Resistive memory devices having a not-and (NAND) structure 有权
标题翻译：具有非 - 和（NAND）结构的电阻式存储器件
公开(公告)号：US08107276B2
公开(公告)日：2012-01-31
申请号：US12631310
申请日：2009-12-04
申请人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
发明人： Matthew J. Breitwisch , Gary S. Ditlow , Michele M. Franceschini , Luis A. Lastras-Montano , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C15/046 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C16/0483 , G11C2013/0088 , G11C2013/0092 , G11C2213/75
摘要： Resistive memories having a not-and (NAND) structure including a resistive memory cell. The resistive memory cell includes a resistive memory element for storing a resistance value and a memory element access device for controlling access to the resistive memory element. The memory element access device is connected in parallel to the resistive memory element.
摘要翻译：具有包括电阻存储单元的非 - 和（NAND）结构的电阻存储器。电阻性存储单元包括用于存储电阻值的电阻性存储器元件和用于控制对电阻式存储器元件的访问的存储元件访问器件。存储元件存取装置与电阻式存储元件并联连接。

84. 发明申请

US20110153533A1 PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN AN ULTRA-DENSE SYNAPSE CROSS-BAR ARRAY 有权
标题翻译：在超声波同步串联阵列阵列中产生依赖时间的塑性
公开(公告)号：US20110153533A1
公开(公告)日：2011-06-23
申请号：US12645479
申请日：2009-12-22
申请人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
发明人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
IPC分类号： G06N3/02
CPC分类号： G06N3/049 , G06N3/0635
摘要： Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.
摘要翻译：本发明的实施方案涉及在用于神经形态系统的超密集突触交叉阵列中产生尖峰时间依赖性可塑性。本发明的一个方面包括当电子神经元尖峰时，警报脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当尖峰电子神经元发出警报脉冲时，门脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当每个电子神经元接收到警报脉冲时，从接收警报脉冲的每个电子神经元发送响应脉冲到尖峰电子神经元。响应脉冲是从接收警报脉冲的电子神经元的最后一次尖峰起的时间的函数。此外，门脉冲和响应脉冲的组合能够增加或降低可变状态电阻器的电导。

85. 发明申请

US20110069538A1 MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE 失效
标题翻译：通过改变复位电压，PCM的多级电容编程
公开(公告)号：US20110069538A1
公开(公告)日：2011-03-24
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

86. 发明申请

US20110024712A1 PCM With Poly-Emitter BJT Access Devices 有权
标题翻译： PCM与多发射器BJT接入设备
公开(公告)号：US20110024712A1
公开(公告)日：2011-02-03
申请号：US12510588
申请日：2009-07-28
申请人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
发明人： Tze-Chiang Chen , Chung Hon Lam , Bipin Rajendran
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L27/2445 , H01L27/2463 , H01L45/06
摘要： A phase change memory (PCM) includes an array comprising a plurality of memory cells, a memory cell comprising a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor. A memory cell for a phase change memory (PCM) includes a phase change element (PCE); and a PCE access device comprising a bipolar junction transistor (BJT), the BJT comprising an emitter region comprising a polycrystalline semiconductor.
摘要翻译：相变存储器（PCM）包括包括多个存储器单元的阵列，包括相变元件（PCE）的存储单元; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。用于相变存储器（PCM）的存储单元包括相变元件（PCE）; 以及包括双极结型晶体管（BJT）的PCE存取装置，所述BJT包括包含多晶半导体的发射极区域。

87. 发明授权

US07602631B2 Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition 有权
标题翻译：利用测量时间延迟作为电平定义的特征参数的多电平存储单元
公开(公告)号：US07602631B2
公开(公告)日：2009-10-13
申请号：US11857356
申请日：2007-09-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C11/565 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/32 , G11C2013/0054
摘要： A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.
摘要翻译：用于操作存储器单元和存储器阵列的存储器阵列和计算机程序产品。本发明的实施例需要接收由存储器单元存储的二进制值。确定操作确定对应于二进制值的目标放电时间。目标放电时间是将预充电电路通过所述存储单元放电至预定水平所需的时间。存储操作将特征参数存储在存储单元中，使得通过至少部分地由存储单元形成的电子电路的电子放电时间基本上等于目标放电时间。

88. 发明申请

US20090175071A1 PHASE CHANGE MEMORY DYNAMIC RESISTANCE TEST AND MANUFACTURING METHODS 有权
标题翻译：相变记忆动态电阻测试和制造方法
公开(公告)号：US20090175071A1
公开(公告)日：2009-07-09
申请号：US11970348
申请日：2008-01-07
申请人： MING-HSIU LEE , Bipin Rajendran , Chung Hon Lam
发明人： MING-HSIU LEE , Bipin Rajendran , Chung Hon Lam
IPC分类号： G11C11/00 , G11C29/00 , G01R31/28
CPC分类号： G11C29/50 , G11C13/0004 , G11C29/50008 , Y10T29/49004
摘要： A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to the sequence of test pulses. A parameter set is extracted from the resistance measurements which includes at least one numerical coefficient that models dependency of the measured resistance on the amplitude of the current through the memory cell. The extracted numerical coefficient or coefficients are associated with the memory device, and used for controlling manufacturing operations.
摘要翻译：用于测试集成电路存储器件的方法包括将测试脉冲序列应用于器件上的存储器单元，其中测试脉冲导致具有取决于测试脉冲的幅度的存储器单元的电流。响应于测试脉冲的顺序测量存储器单元中的电阻。从电阻测量中提取参数集，其包括至少一个数值系数，其模拟所测量的电阻对通过存储器单元的电流的振幅的依赖性。提取的数值系数或系数与存储器件相关联，并用于控制制造操作。

89. 发明申请

US20090073790A1 MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
标题翻译：多级存储单元利用测量时间延迟作为等级定义的特征参数
公开(公告)号：US20090073790A1
公开(公告)日：2009-03-19
申请号：US11857332
申请日：2007-09-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C7/00
CPC分类号： G11C11/565 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
摘要翻译：一种用于操作存储单元和存储器阵列的方法。存储单元操作的方法需要接收读取存储在存储单元中的二进制值的请求。预充电操作将由存储器单元形成的电子电路中的位线电容器预先充电到预充电电压。然后激活电子电路中的字线。放电操作通过电子电路中的所述存储单元将位线电容器放电到字线。此外，当字线被激活时，电子放电时间测量开始。当位线中的电压电平低于预定义的参考电压时，停止电子放电时间测量。确定操作根据测量的电子放电时间确定二进制值。

90. 发明授权

US08898097B2 Reconfigurable and customizable general-purpose circuits for neural networks 有权
标题翻译：可重构和可定制的神经网络通用电路
公开(公告)号：US08898097B2
公开(公告)日：2014-11-25
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译：提供可重构神经网络电路。可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。电路还包括用于重新配置突触阵列的控制模块。控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

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