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    • 81. 发明授权
    • Variable length instruction decoder
    • 可变长度指令解码器
    • US06425070B1
    • 2002-07-23
    • US09044086
    • 1998-03-18
    • Qiuzhen ZouGilbert C. SihInyup KangQuaeed MotiwalaDeepu JohnLi ZhangHaitao ZhangWay-Shing Lee
    • Qiuzhen ZouGilbert C. SihInyup KangQuaeed MotiwalaDeepu JohnLi ZhangHaitao ZhangWay-Shing Lee
    • G06F9302
    • G06F9/3816G06F9/30014G06F9/30098G06F9/30149G06F9/30152G06F9/3885G06F15/7857
    • The present invention is a novel and improved method and circuit for digital signal processing. One aspect of the invention calls for the use of a variable length instruction set. A portion of the variable length instructions may be stored in adjacent locations within memory space with the beginning and ending of instructions occurring across memory word boundaries. Furthermore, additional aspects of the invention are realized by having instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation, or operations, to be performed allowing multiple operations during each clock cycle. Thus, multiple operations are performed during each clock cycle, reducing the total number of clock cycles necessary to perform a task. The exemplary DSP includes a set of three data buses over which data may be exchanged with a register bank and three data memories. The use of more than two data buses, and especially three data buses, realizes another aspect of the invention, which is significantly reduced bus contention. One embodiment of the invention calls for the data buses to include one wide bus and two narrow buses. The wide bus is coupled to a wide data memory and the two narrow buses are coupled to two narrow data memories. Another aspect of the invention is realized by the use of a register bank that has registers accessible by at least two processing units. This allows multiple operations to be performed on a particular set of data by the multiple processing units, without reading and writing the data to and from a memory. The processing units in the exemplary embodiment of the invention include an arithmetic logic (ALU) and a multiply-accumulate (MAC) unit. When combined with the use of the multiple bus architecture, highly parallel instructions, or both, an additional aspect of the invention is realized where highly pipelined, multi-operation, processing is performed.
    • 本发明是用于数字信号处理的新颖且改进的方法和电路。 本发明的一个方面要求使用可变长度指令集。 可变长度指令的一部分可以存储在存储器空间内的相邻位置,同时跨越存储器字边界的指令的开始和结束。 此外,通过使指令包含可变数量的指令片段来实现本发明的附加方面。 每个指令片段导致执行特定操作或操作,允许在每个时钟周期期间进行多个操作。 因此,在每个时钟周期期间执行多个操作,减少执行任务所需的总时钟周期数。 示例性DSP包括一组三个数据总线,数据可以通过该数据总线与寄存器组和三个数据存储器交换。 使用两条以上的数据总线,特别是三条数据总线,实现了本发明的另一方面,这显着减少了总线竞争。 本发明的一个实施例要求数据总线包括一个宽的总线和两个窄的总线。 宽总线耦合到宽数据存储器,并且两个窄总线耦合到两个窄数据存储器。 通过使用具有可由至少两个处理单元访问的寄存器的寄存器组来实现本发明的另一方面。 这允许通过多个处理单元对特定数据集执行多个操作,而不向存储器读取和写入数据。 本发明的示例性实施例中的处理单元包括算术逻辑(ALU)和乘法累加(MAC)单元。 当结合使用多总线架构,高度并行指令或两者时,实现本发明的另一方面,其中执行高度流水线化,多操作的处理。