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81. 发明授权

US06597625B2 Semiconductor memory device 有权
公开(公告)号：US06597625B2
公开(公告)日：2003-07-22
申请号：US09976113
申请日：2001-10-15
申请人： Takanobu Suzuki , Takeshi Hamamoto
发明人： Takanobu Suzuki , Takeshi Hamamoto
IPC分类号： G11C800
CPC分类号： G11C8/06
摘要： A semiconductor memory device wherein, if an address-input buffer section 3 is arranged away from a central part of a memory chip 8, then a second address-latch circuit section 5 is arranged at a neighborhood of the address-input buffer section 3. By this means, the deterioration of the setup/hold characteristics in the address data IA[0-12] of the internal address signal due to coupling noise between wiring lines and the like can be prevented. A first address-latch circuit section 4 is arranged at a central part of the memory chip 8, so that delays in a bank-control signal for memory banks 2a to 2d and the like can be prevented. Further, if the address-input buffer section 3 is divided into a plurality of address-input buffers, for example, two buffers 3a and 3b, and arranged on the memory chip 8, then the second address-latch circuit section 5 is also divided into two address-latch circuits 5a and 5b, corresponding to the address-input buffers 3a and 3b, and the address-latch circuit 5a is arranged at a neighborhood of the address-input buffer 3a, and the address-latch circuit 5b is arranged at a neighborhood of the address-input buffer 3b.

82. 发明授权

US06505325B1 Pattern data density inspection apparatus and density inspection method and recording medium storing pattern data density inspection program 失效
标题翻译：图案数据密度检查装置和密度检查方法以及存储图案数据密度检查程序的记录介质
公开(公告)号：US06505325B1
公开(公告)日：2003-01-07
申请号：US09615450
申请日：2000-07-13
申请人： Takeshi Hamamoto
发明人： Takeshi Hamamoto
IPC分类号： G06F945
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A pattern density inspection apparatus is provided which improves the detection accuracy of a pattern data density error region, and outputs detection results for a designer to efficiently perform a correction operation without performing detection of pattern data density error regions which do not require correction. A control section 1 reads out layout data from a layout storage section 2, and stores this in an input processing section 3 and an output processing section 7. A data density computation processing section 4, while displacing layout data of the input processing section 3 from a position where pattern data was computed immediately before, in either one of an X axis direction and a Y axis direction, performs computations of the pattern density in the detection range after movement, and judges if the pattern data density is above 50%, and makes that above 50% a temporary error region. An error overlap removal processing section 5 takes a logical sum of temporary error regions, and creates an aggregate temporary error region. An error region width computation processing section 6 judges if an aggregate temporary error region is an error shape which contains a 400 &mgr;m square error judgment reference shape.
摘要翻译：提供了图案密度检查装置，其提高了图案数据密度误差区域的检测精度，并且输出检测结果以使设计者有效地执行校正操作，而不执行不需要校正的图案数据密度误差区域的检测。控制部分1从布局存储部分2读出布局数据，并将其存储在输入处理部分3和输出处理部分7中。数据密度计算处理部分4在将输入处理部分3的布局数据从在X轴方向和Y轴方向中的任意一个之前立即计算图案数据的位置，进行运动后的检测范围内的图案密度的计算，判断图案数据密度是否在50％以上，使超过50％的临时错误区域。错误重叠移除处理部分5获取临时错误区域的逻辑和，并创建聚合临时错误区域。误差区域宽度计算处理部6判断聚合暂时错误区域是否包含400μm的平方误差判定基准形状的误差形状。

83. 发明授权

US06377512B1 Clock synchronous type semiconductor memory device that can switch word configuration 有权
标题翻译：时钟同步型半导体存储器件可以切换字配置
公开(公告)号：US06377512B1
公开(公告)日：2002-04-23
申请号：US09666133
申请日：2000-09-20
申请人： Takeshi Hamamoto , Takuya Ariki , Mikio Asakura , Takayuki Nishiyama
发明人： Takeshi Hamamoto , Takuya Ariki , Mikio Asakura , Takayuki Nishiyama
IPC分类号： G11C818
CPC分类号： G11C8/12 , G11C7/1006 , G11C7/1051 , G11C7/1072
摘要： Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.
摘要翻译：数据总线与焊盘一一对应地布置。这些数据总线被共同布置成多个存储器阵列。读数据驱动器根据字配置选择性地被有效地切换以切换存储器阵列和数据总线之间的连接。

84. 发明授权

US06343035B1 Semiconductor device allowing switchable use of internal data buses 失效
标题翻译：允许切换使用内部数据总线的半导体器件
公开(公告)号：US06343035B1
公开(公告)日：2002-01-29
申请号：US09708607
申请日：2000-11-09
申请人： Takashi Kubo , Jun Setogawa , Takeshi Hamamoto
发明人： Takashi Kubo , Jun Setogawa , Takeshi Hamamoto
IPC分类号： G11C700
CPC分类号： G11C7/1006
摘要： When a first data bus line and a second data bus line as a pair are used as a complementary bus, a complementary data signal ZDATA1 is provided to the second data bus line, and an output buffer circuit that becomes unnecessary is rendered inactive. On the other hand, when the first and second data bus lines are used as two single data buses, a differential amplifier transmits two data signals without amplification to the first and second data bus lines. A data signal DATA2 is provided to the second data bus line. The output buffer circuit is activated, and a data signal ZDATA2 is output from an output node.
摘要翻译：当作为一对的第一数据总线和第二数据总线作为互补总线时，互补数据信号ZDATA1被提供给第二数据总线，而不需要的输出缓冲电路变为无效。另一方面，当第一和第二数据总线用作两个单个数据总线时，差分放大器将第二和第二数据总线不经放大地发送两个数据信号。数据信号DATA2被提供给第二数据总线。输出缓冲电路被激活，从输出节点输出数据信号ZDATA2。

85. 发明授权

US06262931B1 Semiconductor memory device having voltage down convertor reducing current consumption 有权
标题翻译：具有降压转换器的半导体存储器件减少电流消耗
公开(公告)号：US06262931B1
公开(公告)日：2001-07-17
申请号：US09539893
申请日：2000-03-31
申请人： Takashi Kono , Kiyohiro Furutani , Takeshi Hamamoto , Katsuyoshi Mitsui
发明人： Takashi Kono , Kiyohiro Furutani , Takeshi Hamamoto , Katsuyoshi Mitsui
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C5/147
摘要： A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.
摘要翻译：控制电路和模式寄存器将响应于每个命令的信号输出到VDC控制电路。 VDC控制电路响应于该命令输出改变存储在VDC中的比较器的直流电流Ic的信号PWRUP。 VDC控制电路根据命令的输入内部产生脉冲宽度对应于规定的延迟时间的信号。因此，通过优选地控制电源电流同时最小化延迟电路和电线的数量，可以不监视每个组的激活，而可以减少电流消耗。

86. 发明授权

US06189129B1 Figure operation of layout for high speed processing 失效
标题翻译：图高速处理布局图
公开(公告)号：US06189129B1
公开(公告)日：2001-02-13
申请号：US09092650
申请日：1998-06-09
申请人： Takeshi Hamamoto
发明人： Takeshi Hamamoto
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： In a method of processing figure arrays in a figure processing apparatus, first and second figure arrays are sequentially inputted. A fractionalizing process is selectively performed to divide each of figure elements of the second figure array into a plurality of types of fractions based on presence/non-presence of an overlapping portion between the first and second figure arrays and an array data of the second figure array. The array data indicates an array pitch in each of horizontal and vertical directions and a number of figures in the direction. A figure array of fractions is produced for each type and the produced figure arrays is registered in chain groups which includes a chain group of the first figure array, such that the registered figure arrays have the same array data. Then, a figure operating process is performed to the chain group.
摘要翻译：在图形处理装置中处理图形阵列的方法中，依次输入第一和第二图形阵列。选择性地执行分数化过程，以基于第一和第二图形数组之间的重叠部分的存在/不存在以及第二图形的阵列数据的不同，将第二图形数组的图形元素中的每一个划分成多种类型的分数数组。阵列数据表示水平和垂直方向中的每一个中的阵列间距和方向上的数量。为每种类型生成图形数组的分数，并且所生成的图形数组被记录在包括第一图形数组的链组的链组中，使得注册的图形数组具有相同的数组数据。然后，对链组进行图形操作处理。

87. 发明授权

US6157588A Semiconductor memory device having hierarchical word line structure 失效
标题翻译：具有分层字线结构的半导体存储器件
公开(公告)号：US6157588A
公开(公告)日：2000-12-05
申请号：US229343
申请日：1999-01-13
申请人： Yasuhiro Matsumoto , Mikio Asakura , Takeshi Hamamoto , Kei Hamade
发明人： Yasuhiro Matsumoto , Mikio Asakura , Takeshi Hamamoto , Kei Hamade
IPC分类号： G11C11/407 , G11C7/18 , G11C11/401 , G11C11/409 , G11C11/4097 , H01L21/8242 , H01L27/108 , G11C7/02
CPC分类号： G11C7/18 , G11C11/4097
摘要： First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.
摘要翻译：第一和第二全局输入/输出线在第一和第二主块之间扭转。第一主块中的第一和第二SD信号线分别布置成与第一和第二全局输入/输出线相邻。第二主块中的第一和第二SD信号线分别布置成与第二和第一全局输入/输出线相邻。为第一或第二SD信号线提供的SD信号对第一和第二全局输入/输出线施加相同的噪声，使得在第一和第二全局输入/输出线之间基本上消除了噪声的影响。因此，全球输入/输出线路具有更高的抗噪声能力，而不会增加布局面积。

88. 发明授权

US6043528A Semiconductor memory device having trench-type capacitor structure using high dielectric film and its manufacturing method 失效
标题翻译：具有使用高介电膜的沟槽型电容器结构的半导体存储器件及其制造方法
公开(公告)号：US6043528A
公开(公告)日：2000-03-28
申请号：US806247
申请日：1997-02-21
申请人： Masami Aoki , Takeshi Hamamoto
发明人： Masami Aoki , Takeshi Hamamoto
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/10873 , Y10S257/908
摘要： A semiconductor memory device comprises a MOS-type transistor formed on a semiconductor substrate, a capacitor formed in the interior of an opening portion formed in the semiconductor substrate to be adjacent to the MOS-type transistor, the capacitor having a capacitor insulating film formed of a high dielectric film, and a line layer for connecting respective gate electrodes of the MOS-type transistor separated to be island-shaped to prevent from being presented on a region where the opening portion is formed, the line layer formed of a conductive layer different from the gate electrodes in its level.
摘要翻译：一种半导体存储器件，包括形成在半导体衬底上的MOS型晶体管，形成在与半导体衬底中形成的与MOS型晶体管相邻的开口部内部的电容器，该电容器具有由高电介质膜和用于连接分离为岛状的MOS型晶体管的各个栅电极的线层，以防止形成在开口部分的区域上，由不同的导电层形成的线层从门电极的电平。

89. 发明授权

US5910927A Memory device and sense amplifier control device 失效
标题翻译：存储器件和读出放大器控制器件
公开(公告)号：US5910927A
公开(公告)日：1999-06-08
申请号：US931525
申请日：1997-09-16
申请人： Takeshi Hamamoto , Masaki Tsukude
发明人： Takeshi Hamamoto , Masaki Tsukude
IPC分类号： G11C11/41 , G11C7/06 , G11C8/10 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C8/12 , G11C7/065 , G11C8/10 , G11C8/14
摘要： A memory device having a smaller circuit area but efficiently used is provided. A plurality of main word lines (MWL) extending in a row direction are connected through respective bank latches (BL) to a single global word line (GWL) extending across banks (BANK0, BANK1). Selective activation of an enable signal (BLE) and the global word line (GWL) selects one of the bank latches (BL) to selectively activate an associated main word line (MWL). This state is held by the selected bank latch (BL) after the enable signal (BLE) is inactivated. Then, another enable signal (BLE) is activated to selectively activate another main word line (MWL). Sub-decoders (SD) connected to the main word lines (MWL) are selected independently of each other to independently activate word lines (WL) for each bank (BANK).
摘要翻译：提供具有较小电路面积但有效使用的存储器件。沿着行方向延伸的多条主字线（MWL）通过相应的存储体锁存器（BL）连接到跨越银行（BANK0，BANK1）延伸的单个全局字线（GWL）。使能信号（BLE）和全局字线（GWL）的选择性激活选择一个存储体锁存器（BL）来选择性地激活相关联的主字线（MWL）。在使能信号（BLE）失效之后，该状态由选择的存储体锁存器（BL）保持。然后，激活另一个使能信号（BLE）以选择性地激活另一主字线（MWL）。连接到主字线（MWL）的子解码器（SD）彼此独立地选择，以独立地激活每个银行（BANK）的字线（WL）。

90. 发明授权

US5731609A MOS random access memory having array of trench type one-capacitor/one-transistor memory cells 失效
公开(公告)号：US5731609A
公开(公告)日：1998-03-24
申请号：US804573
申请日：1997-02-24
申请人： Takeshi Hamamoto , Fumio Horiguchi
发明人： Takeshi Hamamoto , Fumio Horiguchi
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/68 , H01L29/92
CPC分类号： H01L27/108 , H01L27/10841
摘要： A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.

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