专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US07867791B2 Manufacturing method of semiconductor device using multiple mask layers formed through use of an exposure mask that transmits light at a plurality of intensities 有权
标题翻译：使用通过使用以多个强度透射光的曝光掩模形成的多个掩模层的半导体器件的制造方法
公开(公告)号：US07867791B2
公开(公告)日：2011-01-11
申请号：US11458266
申请日：2006-07-18
申请人： Hideto Ohnuma , Masayuki Sakakura
发明人： Hideto Ohnuma , Masayuki Sakakura
IPC分类号： H01L21/00
CPC分类号： H01L27/127 , H01L21/0273 , H01L27/1214 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L27/3244 , H01L27/3276 , H01L51/5237 , H01L51/5246 , H01L51/5259
摘要： The invention provides a technique to manufacture a highly reliable semiconductor device and a display device at high yield. As an exposure mask, an exposure mask provided with a diffraction grating pattern or an auxiliary pattern formed of a semi-transmissive film with a light intensity reducing function is used. With such an exposure mask, various light exposures can be more accurately controlled, which enables a resist to be processed into a more accurate shape. Therefore, when such a mask layer is used, the conductive film and the insulating film can be processed in the same step into different shapes in accordance with desired performances. As a result, thin film transistors with different characteristics, wires in different sizes and shapes, and the like can be manufactured without increasing the number of steps.
摘要翻译：本发明提供了以高产率制造高度可靠的半导体器件和显示器件的技术。作为曝光掩模，使用设置有衍射光栅图案的曝光掩模或由具有光强度降低功能的半透射膜形成的辅助图案。通过这种曝光掩模，可以更精确地控制各种光照射，这使得抗蚀剂能够被加工成更准确的形状。因此，当使用这种掩模层时，导电膜和绝缘膜可以根据期望的性能在同一步骤中被加工成不同的形状。结果，可以在不增加步数的情况下制造具有不同特性的薄膜晶体管，不同尺寸和形状的导线等。

82. 发明授权

US07727846B2 Method of manufacturing an SOI substrate and method of manufacturing a semiconductor device 失效
标题翻译：制造SOI衬底的方法和制造半导体器件的方法
公开(公告)号：US07727846B2
公开(公告)日：2010-06-01
申请号：US12213137
申请日：2008-06-16
申请人： Hideto Ohnuma , Ryota Imahayashi , Yoichi Iikubo , Kenichiro Makino , Sho Nagamatsu
发明人： Hideto Ohnuma , Ryota Imahayashi , Yoichi Iikubo , Kenichiro Makino , Sho Nagamatsu
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L27/1266 , H01L21/76254 , H01L27/1214 , H01L29/78654
摘要： It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.
摘要翻译：本发明的一个目的是提供一种制造具有单晶半导体层的SOI衬底的方法，即使当具有低耐热温度的衬底如玻璃衬底或并且进一步通过使用这种SOI衬底制造具有高可靠性的半导体器件。将与半导体基板分离并与具有绝缘面的支撑基板接合的半导体层用电磁波照射，对半导体层的表面进行抛光处理。半导体层的区域的至少一部分通过电磁波的照射而熔融，能够降低半导体层的晶体缺陷。此外，半导体层的表面可以通过抛光处理被抛光和平坦化。

83. 发明授权

US07700947B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07700947B2
公开(公告)日：2010-04-20
申请号：US11086366
申请日：2005-03-23
申请人： Hideto Ohnuma
发明人： Hideto Ohnuma
IPC分类号： H01L29/04
CPC分类号： H01L27/12 , H01L27/1277 , H01L29/66757 , H01L29/78675 , H01L29/78684
摘要： A metallic element is effectively removed from a semiconductor film crystallized by using the metallic element. The concentration distribution of phosphorous or antimony in the depth direction of at least one of a source and a drain of a TFT semiconductor film has: a region in which the concentration is 1×1020 atoms/cm3 or less is 5 nm or greater in thickness, and 5×1019 atoms/cm3 or greater in the maximum value. By creating this concentration distribution, and by thermal annealing at about between 500 and 650° C., the metallic element within a channel forming region diffuses to the source or the drain, and at the same time as gettering is accomplished, the region in which the concentration is 1×1020 atoms/cm3 or less is made into a nucleus and the source region/drain region is recrystallized.
摘要翻译：有效地从通过使用金属元件结晶的半导体膜去除金属元素。在TFT半导体膜的源极和漏极中的至少一个的深度方向上的磷或锑的浓度分布具有：浓度为1×1020原子/ cm3以下的区域的厚度为5nm以上，最大值为5×1019 atoms / cm3以上。通过产生这种浓度分布，并且通过在约500和650℃之间的热退火，沟道形成区域内的金属元素扩散到源极或漏极，并且在完成吸气的同时，其中将浓度为1×1020原子/ cm3以下制成核，源区/漏区重结晶。

84. 发明授权

US07687404B2 Method for manufacturing display device 有权
标题翻译：显示装置制造方法
公开(公告)号：US07687404B2
公开(公告)日：2010-03-30
申请号：US11121073
申请日：2005-05-04
申请人： Shunpei Yamazaki , Hideto Ohnuma , Mitsuaki Osame , Aya Anzai , Hiromichi Godo , Tomoya Futamura
发明人： Shunpei Yamazaki , Hideto Ohnuma , Mitsuaki Osame , Aya Anzai , Hiromichi Godo , Tomoya Futamura
IPC分类号： H01L21/302
CPC分类号： H01L51/5262 , H01L27/1248 , H01L27/3244 , H01L27/3248 , H01L27/3258
摘要： In a method for manufacturing a display device having a light emitting element, a first base insulating film, a second base insulating film, a semiconductor layer, and a gate insulating film are formed in this order over a substrate. A gate electrode is formed over the gate insulating film to overlap with at least a part of the semiconductor layer, and a portion to be a pixel portion of the gate insulating film and the second base insulating film is doped with at least one conductive type impurities. An opening portion is formed by selectively etching the gate insulating film and second base insulating film that are each doped with impurities. The first base insulating film is exposed in a bottom face of the opening portion. Subsequently, an insulating film is formed to cover the opening portion, the gate insulating film, and the gate electrode, and a light emitting element is formed over the insulating film to overlap with at least a part of the opening portion.
摘要翻译：在具有发光元件的显示装置的制造方法中，在衬底上依次形成第一基底绝缘膜，第二基底绝缘膜，半导体层和栅极绝缘膜。栅极电极形成在栅极绝缘膜上方以与半导体层的至少一部分重叠，栅极绝缘膜和第二基底绝缘膜的像素部分的一部分被掺杂有至少一种导电类型的杂质。通过选择性地蚀刻各自掺杂有杂质的栅极绝缘膜和第二基底绝缘膜来形成开口部。第一基底绝缘膜在开口部的底面露出。随后，形成绝缘膜以覆盖开口部分，栅极绝缘膜和栅电极，并且在绝缘膜上形成发光元件以与开口部分的至少一部分重叠。

85. 发明授权

US07678668B2 Manufacturing method of SOI substrate and manufacturing method of semiconductor device 有权
标题翻译： SOI衬底的制造方法和半导体器件的制造方法
公开(公告)号：US07678668B2
公开(公告)日：2010-03-16
申请号：US12213271
申请日：2008-06-17
申请人： Akihisa Shimomura , Hideto Ohnuma , Tetsuya Kakehata , Kenichiro Makino
发明人： Akihisa Shimomura , Hideto Ohnuma , Tetsuya Kakehata , Kenichiro Makino
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： It is object to provide a manufacturing method of an SOI substrate provided with a single-crystal semiconductor layer, even in the case where a substrate having a low allowable temperature limit, such as a glass substrate, is used and to manufacture a high-performance semiconductor device using such an SOI substrate. Light irradiation is performed on a semiconductor layer which is separated from a semiconductor substrate and bonded to a support substrate having an insulating surface, using light having a wavelength of 365 nm or more and 700 nm or less, and a film thickness d (nm) of the semiconductor layer which is irradiated with the light is made to satisfy d=λ/2n×m±α (nm), when a light wavelength is λ (nm), a refractive index of the semiconductor layer is n, m is a natural number greater than or equal to 1 (m=1, 2, 3, 4, . . . ), and 0≦α≦10 is satisfied.
摘要翻译：目的在于提供一种具有单晶半导体层的SOI衬底的制造方法，即使使用诸如玻璃衬底等具有低允许温度极限的衬底并制造高性能使用这种SOI衬底的半导体器件。使用波长365nm以上且700nm以下的光和膜厚d（nm）在与半导体基板分离并与具有绝缘面的支撑基板接合的半导体层上进行光照射，被照射到半导体层的半导体层的折射率为n时，满足d =λ/ 2n×m±α（nm），当光波长为λ（nm）时，m为大于或等于1（m = 1,2,3,4，...），0＆nlE;α＆nlE; 10的自然数。

86. 发明申请

US20100015764A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100015764A1
公开(公告)日：2010-01-21
申请号：US12512075
申请日：2009-07-30
申请人： Hideto Ohnuma , Shigeharu Monoe , Shunpei Yamazaki
发明人： Hideto Ohnuma , Shigeharu Monoe , Shunpei Yamazaki
IPC分类号： H01L21/336 , H01L21/86
CPC分类号： H01L27/1214 , H01L27/124 , H01L27/1288 , H01L29/66757 , H01L29/78624
摘要： The present invention provides a TFT including at least one LDD region in a self-alignment manner without forming a sidewall spacer and increasing the number of manufacturing steps. A photomask or a reticle provided with an assist pattern that is formed of a diffraction grating pattern or a semi-transmitting film and has a function of reducing light intensity is employed in a photolithography step of forming a gate electrode, an asymmetrical resist pattern having a region with a thick thickness and a region with a thickness thinner than that of the above region on one side is formed, a gate electrode having a stepped portion is formed, and an LDD region is formed in a self-alignment manner by injecting an impurity element to the semiconductor layer through the region with a thin thickness of the gate electrode.
摘要翻译：本发明提供一种TFT，其以自对准方式提供至少一个LDD区域，而不形成侧壁间隔物并增加制造步骤的数量。在形成栅电极的光刻步骤中使用具有由衍射光栅图案或半透射膜形成的辅助图案并具有降低光强度的功能的光掩模或掩模版，具有形成厚度厚的区域和具有比一面上述区域的厚度薄的区域，形成具有台阶部分的栅电极，并且通过注入杂质以自对准方式形成LDD区域元件通过具有薄的栅电极厚度的区域到半导体层。

87. 发明授权

US07635895B2 Display device 失效
标题翻译：显示设备
公开(公告)号：US07635895B2
公开(公告)日：2009-12-22
申请号：US11647179
申请日：2006-12-29
申请人： Hongyong Zhang , Yasuhiko Takemura , Toshimitsu Konuma , Hideto Ohnuma , Naoaki Yamaguchi , Hideomi Suzawa , Hideki Uochi
发明人： Hongyong Zhang , Yasuhiko Takemura , Toshimitsu Konuma , Hideto Ohnuma , Naoaki Yamaguchi , Hideomi Suzawa , Hideki Uochi
IPC分类号： H01L27/12
CPC分类号： H01L27/127 , H01L27/1214 , H01L29/66757 , H01L29/78621 , H01L29/78627
摘要： There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.
摘要翻译：提供了一种方法，通过该方法可以容易地形成轻掺杂漏极（LDD）区域，并且在具有覆盖有氧化物覆盖层的栅电极的薄膜晶体管中的源/漏区域中以良好的产率形成。通过以栅极电极作为掩模，以自对准的方式将杂质引入岛状硅膜中形成轻掺杂漏极（LDD）区域。首先，通过使用旋转 - 倾斜离子注入在岛状硅膜中形成低浓度杂质区，以相对于衬底从倾斜方向进行离子掺杂。此时也在栅电极下方形成低浓度杂质区。之后，将高浓度的杂质通常引入衬底，从而形成高浓度杂质区域。在上述过程中，低浓度杂质区域保留在栅电极下方并构成轻掺杂漏区。

88. 发明授权

US07625786B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07625786B2
公开(公告)日：2009-12-01
申请号：US11088888
申请日：2005-03-25
申请人： Naoki Makita , Misako Nakazawa , Hideto Ohnuma , Takuya Matsuo
发明人： Naoki Makita , Misako Nakazawa , Hideto Ohnuma , Takuya Matsuo
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02672 , H01L21/02686 , H01L27/1277 , H01L29/78612 , H01L29/78621
摘要： Problems in prior art regarding an n-channel TFT in the source/drain gettering method are solved. In the n-channel TFT, its source/drain regions contain only an n-type impurity. Therefore, compared to a p-channel TFT whose source/drain regions contain an n-type impurity and a higher concentration of p-type impurity, the gettering efficiency is inferior in a channel region of the n-channel transistor. Accordingly, the problem of inferior gettering efficiency in the n-channel TFT can be solved by providing at an end of its source/drain regions a highly efficient gettering region that contains an n-type impurity and a p-type impurity both with the concentration of the p-type impurity set higher than the concentration of the n-type impurity.
摘要翻译：解决了在源极/漏极吸杂方法中关于n沟道TFT的现有技术中的问题。在n沟道TFT中，其源极/漏极区仅包含n型杂质。因此，与源极/漏极区域包含n型杂质和较高浓度的p型杂质的p沟道TFT相比，n沟道晶体管的沟道区域的吸杂效率较差。因此，可以通过在其源极/漏极区域的末端设置包含n型杂质的高效吸气区域和浓度为p型的p型杂质来解决n沟道TFT的吸杂效率差的问题的p型杂质的浓度高于n型杂质浓度。

89. 发明授权

US07622336B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07622336B2
公开(公告)日：2009-11-24
申请号：US11645521
申请日：2006-12-27
申请人： Hideto Ohnuma
发明人： Hideto Ohnuma
IPC分类号： H01L21/00 , H01L21/84 , H01L21/44
CPC分类号： H01L27/1288 , H01L21/266 , H01L21/76816 , H01L21/84 , H01L23/5227 , H01L27/1214 , H01L2924/0002 , H01L2924/00
摘要： To provide a manufacturing method of a semiconductor device with a reduced chip area by reducing the size of a pattern for forming an integrated circuit. For example, the size of an IC chip that is provided as an application of IC cards or IC tags can be reduced. The manufacturing method includes the steps of forming a gate electrode; forming an insulating layer over the gate electrode; and forming an opening in the insulating layer. One or both of the step of forming the gate electrode and the step of forming the opening in the insulating layer is/are conducted by a lithography process using a phase-shift mask or a hologram mask. Accordingly, micropatterns can be formed even over a substrate with low planarity such as a glass substrate.
摘要翻译：为了通过减小用于形成集成电路的图案的尺寸来提供具有减小的芯片面积的半导体器件的制造方法。例如，可以减少作为IC卡或IC标签的应用而提供的IC芯片的尺寸。制造方法包括形成栅电极的步骤; 在栅电极上形成绝缘层; 并在所述绝缘层中形成开口。通过使用相移掩模或全息掩模的光刻工艺来进行形成栅电极的步骤和在绝缘层中形成开口的步骤中的一个或两个。因此，甚至可以在具有低平面性的基板上形成微图案，例如玻璃基板。

90. 发明申请

US20090057726A1 Manufacturing method of semiconductor device, semiconductor device, and electronic device 有权
标题翻译：半导体器件，半导体器件和电子器件的制造方法
公开(公告)号：US20090057726A1
公开(公告)日：2009-03-05
申请号：US12230331
申请日：2008-08-27
申请人： Hideto Ohnuma , Shunpei Yamazaki
发明人： Hideto Ohnuma , Shunpei Yamazaki
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/12 , H01L29/045
摘要： An embrittlement layer is formed in a single crystal semiconductor substrate having a (110) plane as a main surface by irradiation of the main surface with ions, and an insulating layer is formed over the main surface of the single crystal semiconductor substrate. The insulating layer and a substrate having an insulating surface are bonded, and the single crystal semiconductor substrate is separated along the embrittlement layer to provide a single crystal semiconductor layer having the (110) plane as a main surface over the substrate having the insulating surface. Then, an n-channel transistor and a p-channel transistor are formed so as to each have a axis of the single crystal semiconductor layer in a channel length direction.
摘要翻译：在具有（110）面作为主表面的单晶半导体衬底中，通过用离子照射主表面，形成脆化层，并且在单晶半导体衬底的主表面上形成绝缘层。绝缘层和具有绝缘表面的基板接合，并且沿着脆化层分离单晶半导体基板，以在具有绝缘表面的基板上提供具有（110）面作为主表面的单晶半导体层。然后，形成n沟道晶体管和p沟道晶体管，使其在沟道长度方向上各自具有单晶半导体层的<110'轴。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式