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81. 发明授权

US07797699B2 Method and apparatus for scheduling virtual machine access to shared resources 有权
标题翻译：调度虚拟机访问共享资源的方法和装置
公开(公告)号：US07797699B2
公开(公告)日：2010-09-14
申请号：US10947902
申请日：2004-09-23
申请人： Alain Kagi , Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Gregory M. Jablonski
发明人： Alain Kagi , Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Gregory M. Jablonski
IPC分类号： G06F9/455 , G06F9/46 , G06F3/00
CPC分类号： G06F9/5011
摘要： A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.
摘要翻译：用于管理来自虚拟机的IO请求以访问物理机器上的IO资源的方法包括确定与IO请求相关联的请求优先级。响应于确定请求优先级，IO请求被放置在适当的队列中。

82. 发明授权

US07257257B2 Method and apparatus for differential, bandwidth-efficient and storage-efficient backups 有权
标题翻译：差分，带宽高效和高效存储备份的方法和设备
公开(公告)号：US07257257B2
公开(公告)日：2007-08-14
申请号：US10644445
申请日：2003-08-19
申请人： Andrew V. Anderson , Steven M. Bennett , Scott H. Robinson
发明人： Andrew V. Anderson , Steven M. Bennett , Scott H. Robinson
IPC分类号： G06K9/00
CPC分类号： G06F11/1464 , G06F11/1451
摘要： A process is introduced that determines contour requirements from many factors. Based on the contour requirements, the process either generates at least one content-derived signature contour from either many content identifiers or at least one content-derived signature contour, or generates at least one optimized content-derived signature contour from contour-related data and either at least one content-derived signature contour or a derivation from at least one content-derived signature contour.
摘要翻译：引入了一个从许多因素确定轮廓要求的过程。基于轮廓要求，该过程或者从许多内容标识符或至少一个内容导出的签名轮廓生成至少一个内容导出签名轮廓，或者从轮廓相关数据生成至少一个优化的内容导出签名轮廓，以及至少一个内容导出的签名轮廓或从至少一个内容导出的签名轮廓的派生。

83. 发明授权

US07139808B2 Method and apparatus for bandwidth-efficient and storage-efficient backups 失效
公开(公告)号：US07139808B2
公开(公告)日：2006-11-21
申请号：US10136756
申请日：2002-04-30
申请人： Andrew V. Anderson , Steven M. Bennett , Scott H. Robinson
发明人： Andrew V. Anderson , Steven M. Bennett , Scott H. Robinson
IPC分类号： G06F15/167 , G06F12/14
CPC分类号： H04L29/06 , H04L67/30 , H04L69/329
摘要： A method is presented that includes generating a content identifier for at least one article. The content identifier identifies the article. Also, determining if at least a portion of the at least one article is present on at least one device based on the content identifier. The at least one portion of the at least one article is stored if the at least one portion of the at least one article is determined to be not present on the at least one device. Also presented is a method including requesting at least one article by a content identifier representing the article. The at least one article is determined if it is present on at least one device based on the content identifier. At least one portion of the at least one article is returned if the at least one portion of the at least one article is determined to be present on the at least one device.

84. 发明授权

US6003111A Bank state tracking method and device 失效
标题翻译：银行状态跟踪方法和设备
公开(公告)号：US6003111A
公开(公告)日：1999-12-14
申请号：US974320
申请日：1997-11-19
申请人： Thomas J. Holman , Andrew V. Anderson
发明人： Thomas J. Holman , Andrew V. Anderson
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0215
摘要： A mechanism for tracking the state of a plurality of memory banks in a memory device includes a register which has a plurality of bits, with each bit corresponding to one of the memory banks in the memory device. An open bank circuit has an output coupled to the register and is responsive to both a bank select signal which identifies a first memory bank and an open signal, to set a register bit associated with the first memory bank. A close bank circuit has an output coupled to the register and is responsive to the bank select signal which identifies a second memory bank as well as a close signal to reset the register bit associated with the second memory bank and any banks adjacent to the second memory bank.
摘要翻译：用于跟踪存储器件中的多个存储体的状态的机构包括具有多个位的寄存器，每个位对应于存储器件中的一个存储体。开路组电路具有耦合到寄存器的输出，并响应识别第一存储体和开启信号的存储体选择信号，以设置与第一存储体相关联的寄存器位。闭路电路具有耦合到寄存器的输出，并且响应于识别第二存储器组的存储体选择信号以及闭合信号以复位与第二存储体相关联的寄存器位和与第二存储器相邻的任何存储体银行。

85. 发明申请

US20160179667A1 INSTRUCTION AND LOGIC FOR FLUSH-ON-FAIL OPERATION 有权
标题翻译： FLUSH-ON-FAIL操作的指导和逻辑
公开(公告)号：US20160179667A1
公开(公告)日：2016-06-23
申请号：US14580632
申请日：2014-12-23
申请人： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
发明人： Sanjay Kumar , Rajesh M. Sankaran , Subramanya R. Dulloor , Andrew V. Anderson
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F9/467 , G06F11/07 , G06F11/073 , G06F11/0778 , G06F11/0793 , G06F11/14 , G06F11/1482 , G06F12/0868 , G06F2201/805 , G06F2201/82 , G06F2212/1032 , G06F2212/608
摘要： A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.
摘要翻译：处理器包括存储器管理单元和包括解码器的前端。解码器包括用于在与FoC指令相关联的存储的承诺时接收刷新提交（FoC）指令以将脏数据从易失性高速缓冲器刷新到持久存储器的逻辑。存储器管理单元包括基于刷新失败（FoF）模式的逻辑，跳过刷新提交指令的执行，并且在随后的FoF操作时从易失性高速缓存清除脏数据。

86. 发明申请

US20140380009A1 PROTECTED MEMORY VIEW FOR NESTED PAGE TABLE ACCESS BY VIRTUAL MACHINE GUESTS 审中-公开
标题翻译：受保护的内存视图，用于虚拟机客户访问的页面表
公开(公告)号：US20140380009A1
公开(公告)日：2014-12-25
申请号：US14127561
申请日：2013-06-24
申请人： Michael Lemay , David M. Durham , Ravi L. Sahita , Andrew V. Anderson
发明人： Michael Lemay , David M. Durham , Ravi L. Sahita , Andrew V. Anderson
IPC分类号： G06F12/14 , G06F9/455 , G06F12/10
CPC分类号： G06F12/145 , G06F9/30076 , G06F9/45558 , G06F12/1009 , G06F12/1491 , G06F2009/45583 , G06F2212/1052 , G06F2212/151
摘要： Generally, this disclosure provides systems, methods and computer readable media for a protected memory view in a virtual machine (VM) environment enabling nested page table access by trusted guest software outside of VMX root mode. The system may include an editor module configured to provide access to a nested page table structure, by operating system (OS) kernel components and by user space applications within a guest of the VM, wherein the nested page table structure is associated with one of the protected memory views. The system may also include a page handling processor configured to secure that access by maintaining security information in the nested page table structure.
摘要翻译：通常，本公开提供了用于虚拟机（VM）环境中的受保护的存储器视图的系统，方法和计算机可读介质，其实现了受VMX根模式之外的受信任客户机的嵌套页表访问。该系统可以包括被配置为通过操作系统（OS）内核组件和由VM的来宾内的用户空间应用提供对嵌套页表结构的访问的编辑器模块，其中嵌套页表结构与受保护的内存视图。该系统还可以包括页面处理处理器，其被配置为通过维护嵌套页表结构中的安全信息来保护该访问。

87. 发明授权

US07836275B2 Method and apparatus for supporting address translation in a virtual machine environment 有权
标题翻译：用于在虚拟机环境中支持地址转换的方法和装置
公开(公告)号：US07836275B2
公开(公告)日：2010-11-16
申请号：US12154627
申请日：2008-05-22
申请人： Andrew V. Anderson , Alain Kägi
发明人： Andrew V. Anderson , Alain Kägi
IPC分类号： G06F21/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/1036 , G06F9/45558 , G06F2009/45583
摘要： In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM. The determination is made based on metadata extracted from a shadow translation data structure maintained by a virtual machine monitor (VMM) and attributes associated with entries in the shadow translation data structure. The method further includes synchronizing entries in the shadow translation data structure that correspond to the modified entries in the guest translation data structure with the modified entries in the guest translation data structure.
摘要翻译：在一个实施例中，一种方法包括接收由于与翻译后备缓冲器（TLB）有关的特权事件而从虚拟机（VM）转换的控制，以及确定客户转换数据结构中哪些条目被VM修改。基于从由虚拟机监视器（VMM）维护的阴影翻译数据结构提取的元数据和与阴影翻译数据结构中的条目相关联的属性进行确定。该方法还包括将客体翻译数据结构中与经修改的条目相对应的影子翻译数据结构中的条目与访客翻译数据结构中的修改的条目同步。

88. 发明授权

US06622087B2 Method and apparatus for deriving travel profiles 有权
公开(公告)号：US06622087B2
公开(公告)日：2003-09-16
申请号：US09748813
申请日：2000-12-26
申请人： Andrew V. Anderson
发明人： Andrew V. Anderson
IPC分类号： G01C2100
CPC分类号： G01C21/3484
摘要： A route request is received from a user to travel from a start location to a destination location. A route guidance is provided for a route to the destination location based on a travel profile for the user in response to the route request. The travel profile comprises one or more of a history of driving behavior of the user and a driving preference specified by the user.

89. 发明授权

US06453393B1 Method and apparatus for interfacing to a computer memory 有权
标题翻译：用于连接到计算机存储器的方法和装置
公开(公告)号：US06453393B1
公开(公告)日：2002-09-17
申请号：US09663918
申请日：2000-09-18
申请人： Thomas J. Holman , Andrew V. Anderson
发明人： Thomas J. Holman , Andrew V. Anderson
IPC分类号： G06F1200
CPC分类号： G06F13/1694
摘要： A memory system includes a primary memory interface, coupled to a primary device, adapted to receive memory requests from the primary device, and to transmit memory device independent requests based on the memory requests from the primary device. An external memory interface is coupled to at least one memory device via a memory interconnect. A memory independent interconnect, coupled to the primary memory interface and the external memory interface, is adapted to transport the memory device independent requests from the primary memory interface to the external memory interface.
摘要翻译：存储器系统包括耦合到主设备的主存储器接口，适于从主设备接收存储器请求，以及基于来自主设备的存储器请求来发送存储设备独立请求。外部存储器接口经由存储器互连耦合到至少一个存储器件。耦合到主存储器接口和外部存储器接口的独立于存储器的互连适于将存储器件独立的请求从主存储器接口传送到外部存储器接口。

90. 发明授权

US06226757B1 Apparatus and method for bus timing compensation 有权
标题翻译：总线定时补偿的装置和方法
公开(公告)号：US06226757B1
公开(公告)日：2001-05-01
申请号：US09169245
申请日：1998-10-09
申请人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
发明人： Frederick A. Ware , Richard M. Barth , Donald C. Stark , Craig E. Hampel , Ely K. Tsern , Abhijit M. Abhyankar , Thomas J. Holman , Andrew V. Anderson , Peter D. MacWilliams
IPC分类号： G06F104
CPC分类号： G06F13/4226
摘要： A digital system includes a clock line carrying a clock signal and a communication bus with a signal time of flight longer than a cycle of the clock signal. A master device is connected to the communication bus and the clock line. The master device selectively applies signals to the communication bus. A set of slave devices are connected to the communication bus and the clock line. Each slave device of the set of slave devices has an associated latency delay arising from its position on the communication bus. Each slave device includes delay circuitry to compensate for the associated latency delay such that the master device observes a uniform minimum latency for each slave device in response to applying signals to the communication bus.
摘要翻译：一个数字系统包括一个带有时钟信号的时钟线和一个具有比时钟信号周期长的信号时间的通信总线。主设备连接到通信总线和时钟线。主设备选择性地向通信总线施加信号。一组从设备连接到通信总线和时钟线。一组从设备的每个从设备具有由其在通信总线上的位置产生的相关联的延迟延迟。每个从设备包括延迟电路以补偿相关联的延迟延迟，使得主设备响应于向通信总线应用信号而观察到每个从设备的均匀最小等待时间。

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