专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06709902B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06709902B2
公开(公告)日：2004-03-23
申请号：US10035205
申请日：2002-01-04
申请人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
发明人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
IPC分类号： H01L2703
CPC分类号： H01L29/66765 , G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78627 , H01L29/78633
摘要： The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.
摘要翻译：本发明提供了一种半导体器件，其中布置在每个电路中的底栅TFT或反向交错TFT适当地构成为与各个电路的功能一致，从而提高了半导体器件的工作效率和可靠性。在该结构中，像素TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的N沟道TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的P沟道TFT中的LDD区域布置成与沟道保护绝缘膜重叠并与栅电极重叠。

82. 发明授权

US09059294B2 Semiconductor device, active matrix substrate, and display device 有权
标题翻译：半导体器件，有源矩阵基板和显示器件
公开(公告)号：US09059294B2
公开(公告)日：2015-06-16
申请号：US13520853
申请日：2010-09-24
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： G06F3/038 , H01L29/786 , H01L27/12 , G02F1/1334 , G02F1/1362 , G02F1/1368 , G09G3/36
CPC分类号： H01L27/1251 , G02F1/1334 , G02F1/13624 , G02F1/1368 , G09G3/3648 , G09G2300/0814 , G09G2300/0819 , G09G2300/0852 , G09G2320/0214 , G09G2320/041 , G09G2330/021 , G09G2340/0435 , G09G2360/144 , H01L27/1214 , H01L29/78633 , H01L29/78645
摘要： A switching circuit (semiconductor device) (18) includes two switching units (SW1 and SW2), which are connected in series to each other, and two capacitances (CS1 and CS2), where one electrode of one of the capacitances is connected to the connecting section of the switching units (SW1 and SW2) and one electrode of the other capacitance is connected to one end of the switching units (SW1 and SW2). To the other electrodes of the capacitances (CS1 and CS2), signals having a constant voltage or signals having a same phase are supplied. A bottom gate electrode (light-shielding film) (22) is formed for the switching unit (SW2).
摘要翻译：开关电路（半导体器件）（18）包括彼此串联连接的两个开关单元（SW1和SW2）和两个电容（CS1和CS2），其中一个电容的一个电极连接到开关单元（SW1和SW2）的连接部分和另一个电容的一个电极连接到开关单元（SW1和SW2）的一端。对于电容（CS1和CS2）的其他电极，提供具有恒定电压的信号或具有相同相位的信号。为开关单元（SW2）形成底栅电极（遮光膜）（22）。

83. 发明申请

US20140138678A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140138678A1
公开(公告)日：2014-05-22
申请号：US14130844
申请日：2012-06-26
申请人： Kazuatsu Ito , Hidehito Kitakado
发明人： Kazuatsu Ito , Hidehito Kitakado
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/66969 , H01L29/78618 , H01L29/78645 , H01L29/78696
摘要： A semiconductor device (100A) has an oxide semiconductor layer (11). The oxide semiconductor layer (11) has a channel region (11c), and a source region (11s) and drain region (11d) positioned on respective sides of the channel region (11c). The source region (11s) has a low-resistance source region (11sx) that has a lower resistance than the channel region (11c), and the drain region (11d) has a low-resistance drain region (11dx) that has a lower resistance than the channel region (11c). The carrier concentrations of the low-resistance source region (11sx) and the low-resistance drain region (11dx) become progressively lower from a connecting portion between a source electrode (17) and the low-resistance source region (11sx) and a connecting portion between a drain electrode (18) and the low-resistance drain region (11dx) towards the channel region (11c).
摘要翻译：半导体器件（100A）具有氧化物半导体层（11）。氧化物半导体层（11）具有沟道区域（11c）以及位于沟道区域（11c）的相应侧面上的源极区域（11s）和漏极区域（11d）。源极区域（11s）具有比沟道区域（11c）低的电阻的低电阻源极区域（11sx），漏极区域（11d）具有低电阻漏极区域（11dx）电阻比通道区域（11c）。低电阻源极区域（11sx）和低电阻漏极区域（11dx）的载流子浓度从源电极（17）和低电阻源极区域（11sx）之间的连接部分逐渐降低，并且连接漏极电极（18）和低电阻漏极区域（11dx）之间的部分朝向沟道区域（11c）。

84. 发明授权

US08648397B2 Semiconductor device, active matrix substrate and display device 有权
标题翻译：半导体器件，有源矩阵基板和显示器件
公开(公告)号：US08648397B2
公开(公告)日：2014-02-11
申请号：US13515921
申请日：2010-11-02
申请人： Seiji Kaneko , Hidehito Kitakado
发明人： Seiji Kaneko , Hidehito Kitakado
IPC分类号： H01L29/80
CPC分类号： H01L29/78633 , G02F1/1368 , H01L29/78621 , H01L29/78645 , H01L29/78648
摘要： A switching element (a semiconductor device) (18) having a top gate electrode (21) and a bottom gate electrode (23) is provided with a silicon layer (a semiconductor layer) (SL) that is arranged between the top gate electrode (21) and the bottom gate electrode (a light-shielding film) (23) and that has a source region (24), a drain region (28), a channel region (26), and low-concentration impurity regions (25, 27). Furthermore, the bottom gate electrode (23) is arranged so as to overlap the channel region (26), a part of the low-concentration impurity region (25), which is adjacent to the source region (24), and a part of the low-concentration impurity region (27), which is adjacent to the drain region (28). The bottom gate electrode (23) is controlled so as to have a prescribed potential.
摘要翻译：具有顶栅极（21）和底栅电极（23）的开关元件（半导体器件）（18）设置有硅层（半导体层）（SL），其设置在顶栅电极 21）和底栅极（遮光膜）（23），并且具有源极区（24），漏极区（28），沟道区（26）和低浓度杂质区（25， 27）。此外，底栅电极（23）被布置成与沟道区（26）重叠，与源区（24）相邻的低浓度杂质区（25）的一部分，和与漏极区域（28）相邻的低浓度杂质区域（27）。底栅极（23）被控制为具有规定的电位。

85. 发明申请

US20140035478A1 THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管及其制造方法及显示装置
公开(公告)号：US20140035478A1
公开(公告)日：2014-02-06
申请号：US14002211
申请日：2012-02-23
申请人： Hidehito Kitakado , Sumio Katoh
发明人： Hidehito Kitakado , Sumio Katoh
IPC分类号： H01L29/786 , H05B37/02 , H01L29/66
CPC分类号： H01L29/7869 , H01L29/45 , H01L29/66742 , H01L29/66969 , H01L29/78618 , H05B37/02
摘要： The invention provides a thin film transistor having current driving force that can be substantially improved. By heat treatment, the IGZO layer (45) from which oxygen is taken away by the titanium electrodes (65) becomes the low resistance regions (40b), and the IGZO layer (45) from which oxygen is not taken away remains as the high resistance region (40a). In this state, when the gate voltage is applied to the gate electrode (20), electrons in the low resistance regions (40b) near the boundaries with the high resistance region (40a) move respectively to the titanium electrode (65) sides. As a result, the length of the low resistance regions (40b) becomes short, and oppositely, the length of the high resistance region (40a) becomes longer by the size of the shortened low resistance regions. However, the electrical channel length (Le) becomes shorter than the source/drain interval space (Lch) as the limit resolution of the exposure device, and the current driving force becomes large.
摘要翻译：本发明提供一种薄膜晶体管，其具有可大大改善的电流驱动力。通过热处理，由钛电极（65）夺取氧的IGZO层（45）成为低电阻区域（40b），并且不吸收氧气的IGZO层（45）保持为高电阻区域（40a）。在该状态下，当栅电极（20）施加栅极电压时，与高电阻区域（40a）的边界附近的低电阻区域（40b）中的电子分别移动到钛电极（65）侧。结果，低电阻区域（40b）的长度变短，相反地，通过缩短的低电阻区域的尺寸，高电阻区域（40a）的长度变长。然而，电通道长度（Le）比作为曝光装置的极限分辨率的源极/漏极间隔空间（Lch）短，并且电流驱动力变大。

86. 发明申请

US20130334530A1 THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE 有权
标题翻译：薄膜晶体管，其制造方法和显示器件
公开(公告)号：US20130334530A1
公开(公告)日：2013-12-19
申请号：US14002794
申请日：2012-03-02
申请人： Sumio Katoh , Hidehito Kitakado
发明人： Sumio Katoh , Hidehito Kitakado
IPC分类号： H01L29/786 , H01L33/00
CPC分类号： H01L29/78693 , H01L27/1222 , H01L29/41733 , H01L29/78609 , H01L29/78618 , H01L29/7869 , H01L29/78696 , H01L33/0041
摘要： The invention provides a thin film transistor that can reduce an off-current flowing in end-parts in a channel width direction of a channel layer and a manufacturing method therefor.Widths of a source electrode (160a) and a drain electrode (160b) are smaller than a width of a channel layer (140). Accordingly, in the channel layer (140), low resistance regions (140b) are formed to surround respectively the source electrode (160a) and the drain electrode (160b). A high resistance region (140a) having a higher resistance value than those of the low resistance regions (140b) remains not only in the region sandwiched between the two low resistance regions (140b), but also in the end parts in the channel width direction. As a result, in a TFT (100), the high resistance region (140a) is extended not only to the channel region sandwiched between the source electrode (160a) and the drain electrode (160b), but also to the end parts in the channel width direction. Accordingly, the off-current flowing through the end parts in the channel width direction reduces.
摘要翻译：本发明提供一种薄膜晶体管及其制造方法，该薄膜晶体管能够减小沟道层的沟道宽度方向的端部流过的截止电流。源电极（160a）和漏电极（160b）的宽度小于沟道层（140）的宽度。因此，在沟道层（140）中，分别形成有低电阻区域（140b）围绕源电极（160a）和漏电极（160b）。具有比低电阻区域（140b）更高的电阻值的高电阻区域（140a）不仅保持在夹在两个低电阻区域（140b）之间的区域中，而且在通道宽度方向上的端部部分。结果，在TFT（100）中，高电阻区域（140a）不仅延伸到夹在源电极（160a）和漏电极（160b）之间的沟道区域，而且延伸到通道宽度方向。因此，在通道宽度方向流过端部的截止电流减少。

87. 发明授权

US08492212B2 Thin-film transistor producing method 有权
标题翻译：薄膜晶体管的制造方法
公开(公告)号：US08492212B2
公开(公告)日：2013-07-23
申请号：US13382448
申请日：2010-02-17
申请人： Tokuaki Kuniyoshi , Hidehito Kitakado , Tadayoshi Miyamoto , Kazuhide Tomiyasu , Sumio Katoh
发明人： Tokuaki Kuniyoshi , Hidehito Kitakado , Tadayoshi Miyamoto , Kazuhide Tomiyasu , Sumio Katoh
IPC分类号： H01L29/66765
CPC分类号： H01L29/78621 , G02F1/1368 , H01L29/4908 , H01L29/66765
摘要： Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.
摘要翻译：提供了一种薄膜晶体管制造方法，通过该方法可以制造具有LDD区的薄膜晶体管，而不增加所使用的光掩模的数量。形成在TFT（10）的多晶硅膜（26）上的蚀刻停止层（35）不仅用作掩模以在通过蚀刻形成源电极和漏电极时保护沟道区（27）而且当离子被注入以形成源/漏区（39）时也作为掩模。因此，离子注入多晶硅膜（26）中以形成源极/漏极区（39）的磷未被植入LDD区（38）中，因此不需要另外形成当植入离子时用作掩模的抗蚀剂图案。

88. 发明授权

US08288831B2 Semiconductor device, method of manufacturing the same, and electronic device having the same 失效
标题翻译：半导体装置及其制造方法以及具有该半导体装置的电子装置
公开(公告)号：US08288831B2
公开(公告)日：2012-10-16
申请号：US12984623
申请日：2011-01-05
申请人： Takeshi Noda , Hidehito Kitakado , Takuya Matsuo
发明人： Takeshi Noda , Hidehito Kitakado , Takuya Matsuo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66757 , H01L29/42384 , H01L29/78603 , H01L29/78621 , H01L29/78675
摘要： A semiconductor device, which can improve the effect of a hydrogenation treatment in case of using a GOLD structure, and a method of manufacturing thereof is provided. A gate insulating film is formed on a semiconductor layer, and a source region, a drain region, and LDD regions are formed in the semiconductor layer. A main gate is formed on the gate insulating film. A sub-gate is formed on the main gate and the gate insulating film so as to cover a part of the main gate and either the LDD regions adjacent to the source region or the drain region. An interlayer insulating film containing hydrogen is formed on the sub-gate, main gate, and gate insulating film. Subsequently, a heat treatment for hydrogenation is performed to terminate a crystal defect of the semiconductor layer with hydrogen.
摘要翻译：提供了可以提高在使用GOLD结构的情况下氢化处理的效果的半导体器件及其制造方法。在半导体层上形成栅极绝缘膜，在半导体层中形成源极区，漏极区，LDD区。在栅极绝缘膜上形成主栅极。在主栅极和栅极绝缘膜上形成子栅极，以覆盖主栅极的一部分和与源极区域或漏极区域相邻的LDD区域。在子栅极，主栅极和栅极绝缘膜上形成含有氢的层间绝缘膜。随后，进行用于氢化的热处理，以氢终止半导体层的晶体缺陷。

89. 发明申请

US20110199329A1 CAPACITANCE CHANGE DETECTING CIRCUIT 审中-公开
标题翻译：电容变化检测电路
公开(公告)号：US20110199329A1
公开(公告)日：2011-08-18
申请号：US12998336
申请日：2009-06-02
申请人： Hidehito Kitakado , Christopher Brown
发明人： Hidehito Kitakado , Christopher Brown
IPC分类号： G06F3/045
CPC分类号： G06F3/044 , G02F1/13338 , G09G3/3648
摘要： When a surface of a liquid crystal panel is pressed, the capacitance value of a variable capacitor changes. In at least one embodiment, one electrode of the variable capacitor is connected to a voltage supply line to which a common voltage is applied, and the other electrode of the variable capacitor is connected to a gate electrode of a TFT. The TFT outputs a voltage generated according to the capacitance value of the variable capacitor. One electrode of a control capacitor is connected to the gate electrode of the TFT, and the other electrode of the control capacitor is connected to a control voltage line to which a control voltage is applied. By applying a control voltage to the gate electrode of the TFT through the control capacitor, while the load capacitance of the control voltage line is reduced and a change in capacitance is detected with a high sensitivity, the sensitivity can be adjusted according to the application, person, etc., when used. By this, a capacitance change detecting circuit is provided that can detect a change in capacitance with a high sensitivity and can control the sensitivity when used.
摘要翻译：当按压液晶面板的表面时，可变电容器的电容值发生变化。在至少一个实施例中，可变电容器的一个电极连接到施加公共电压的电压供给线，可变电容器的另一个电极连接到TFT的栅电极。 TFT输出根据可变电容器的电容值产生的电压。控制电容器的一个电极连接到TFT的栅电极，控制电容器的另一个电极连接到施加控制电压的控制电压线。通过控制电容器向TFT的栅电极施加控制电压，在控制电压线的负载电容降低并且以高灵敏度检测电容变化的同时，可以根据应用来调整灵敏度，人等，使用时。由此，提供了能够以高灵敏度检测电容变化并且可以在使用时控制灵敏度的电容变化检测电路。

90. 发明申请

US20110193816A1 CAPACITANCE CHANGE DETECTING CIRCUIT 审中-公开
标题翻译：电容变化检测电路
公开(公告)号：US20110193816A1
公开(公告)日：2011-08-11
申请号：US12998312
申请日：2009-06-02
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： G06F3/044 , G06F3/038
CPC分类号： G06F3/044 , G06F3/0412 , G09G3/3648
摘要： In at least one embodiment, when a surface of a liquid crystal panel is pressed, the capacitance value of a variable capacitor changes. One electrode of the variable capacitor is connected to a voltage supply line to which a common voltage is applied, and the other electrode of the variable capacitor is connected to a gate electrode of a TFT. The TFT outputs a voltage generated according to the capacitance value of the variable capacitor. Another TFT is provided between a control voltage line to which a control voltage is applied and the gate electrode of the TFT. A gate electrode of the other TFT is connected to a row selection line. By providing the other TFT, a desired voltage is applied to the gate electrode of the TFT, whereby charge accumulated on the electrode is dissipated, enabling to prevent circuit malfunction. By reducing the load capacitance of the control voltage line, a change in capacitance can be detected with a high sensitivity. By this, a capacitance change detecting circuit is provided that can detect a change in capacitance with a high sensitivity without malfunction.
摘要翻译：在至少一个实施例中，当按压液晶面板的表面时，可变电容器的电容值发生变化。可变电容器的一个电极连接到施加公共电压的电压供给线，并且可变电容器的另一个电极连接到TFT的栅电极。 TFT输出根据可变电容器的电容值产生的电压。在施加控制电压的控制电压线和TFT的栅电极之间设置另一TFT。另一个TFT的栅电极连接到行选择线。通过提供另一TFT，期望的电压被施加到TFT的栅电极，由此累积在电极上的电荷消散，从而能够防止电路故障。通过降低控制电压线的负载电容，可以高灵敏度地检测电容的变化。由此，提供了能够以高灵敏度无故障地检测电容的变化的电容变化检测电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式