会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 86. 发明授权
    • Logic circuit and semiconductor device
    • 逻辑电路和半导体器件
    • US08400187B2
    • 2013-03-19
    • US12901057
    • 2010-10-08
    • Shunpei YamazakiJun KoyamaMasashi TsubukuKosei Noda
    • Shunpei YamazakiJun KoyamaMasashi TsubukuKosei Noda
    • H01L25/00H03K19/094H03B1/00
    • H01L29/7869H01L22/34H01L27/0207H01L27/1225H01L29/78696H01L2924/0002H01L2924/00
    • A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
    • 逻辑电路包括具有使用氧化物半导体形成的沟道形成区域的薄膜晶体管,以及通过关闭薄膜晶体管而使端子中的一个成为浮置状态的电容器。 氧化物半导体的氢浓度为5×1019(原子/ cm3)以下,因此在不产生电场的状态下基本上用作绝缘体。 因此,可以减小薄膜晶体管的截止电流,从而通过薄膜晶体管抑制存储在电容器中的电荷的泄漏。 因此,可以防止逻辑电路的故障。 此外,可以通过减小薄膜晶体管的截止电流来降低在逻辑电路中流动的过量的电流,导致逻辑电路的低功耗。
    • 87. 发明授权
    • Semiconductor device and manufacturing method thereof
    • 半导体装置及其制造方法
    • US08389417B2
    • 2013-03-05
    • US12945516
    • 2010-11-12
    • Shunpei YamazakiJun Koyama
    • Shunpei YamazakiJun Koyama
    • H01L21/302H01L21/461
    • H01L27/1207H01L21/8221H01L27/0688H01L27/1225H01L29/24
    • An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.
    • 目的是提供具有新颖结构的半导体器件。 半导体器件包括第一晶体管,其包括设置在包括半导体材料的衬底中的沟道形成区域,杂质区域,第一栅极绝缘层,第一栅极电极和第一源极电极以及第一漏极电极, 第二晶体管,其包括在包括半导体材料的衬底上的氧化物半导体层,第二源电极和第二漏电极,第二栅极绝缘层和第二栅电极。 第二源电极和第二漏极包括通过氧化其侧表面而形成的氧化物区域,并且第一栅电极,第一源电极和第一漏极电极中的至少一个电连接到 第二栅电极,第二源电极和第二漏电极。
    • 90. 发明申请
    • Display Device
    • 显示设备
    • US20120326951A1
    • 2012-12-27
    • US13529129
    • 2012-06-21
    • Shunpei YamazakiJun KoyamaHiroyuki Miyake
    • Shunpei YamazakiJun KoyamaHiroyuki Miyake
    • G09G3/30
    • G02F1/1345
    • To provide a display device with little signal delay and a display device that can operate with low power consumption, parasitic capacitance between a common wiring that applies a common potential to a plurality of pixels and signal lines that input signals for driving the pixels is avoided. Specifically, the common wiring is routed outwardly with respect to an external input terminal to which a signal is input from the, outside, to avoid intersections of the signal lines and the common wiring. Thus, parasitic capacitance between the common wiring and the signal lines is avoided, so that the display device can operate at high speed with low power consumption.
    • 为了提供几乎没有信号延迟的显示装置和能够以低功耗工作的显示装置,避免了对多个像素施加共同电位的公共布线与输入用于驱动像素的信号的信号线之间的寄生电容。 具体地,公共布线相对于从外部输入信号的外部输入端子向外布线,以避免信号线和公共布线的交叉。 因此,避免了公共布线和信号线之间的寄生电容,使得显示装置能够以低功耗高速运行。