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81. 发明授权

US07315471B2 Semiconductor memory device for storing multivalued data 有权
标题翻译：用于存储多值数据的半导体存储器件
公开(公告)号：US07315471B2
公开(公告)日：2008-01-01
申请号：US11469279
申请日：2006-08-31
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621 , G11C2211/5646 , G11C2211/5648 , G11C2216/14
摘要： Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
摘要翻译：数据存储电路以一一对应的方式连接到位线。写电路将第一页上的数据写入由字线同时选择的多个第一存储单元。此后，写电路将第二页上的数据写入多个第一存储单元。然后，写入电路将第一和第二页面上的数据写入与位线方向相邻的第一存储单元的第二存储单元。

82. 发明授权

US07310270B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07310270B2
公开(公告)日：2007-12-18
申请号：US11737154
申请日：2007-04-19
申请人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
发明人： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
摘要翻译： NAND单元单元包括串联连接的存储单元。对所有存储单元进行擦除操作。然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选择的存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极记忆细胞因此数据被编程到所选择的存储单元中。根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

83. 发明授权

US07307881B2 Non-volatile semiconductor memory with large erase blocks storing cycle counts 有权
标题翻译：具有存储循环计数的大擦除块的非易失性半导体存储器
公开(公告)号：US07307881B2
公开(公告)日：2007-12-11
申请号：US11004139
申请日：2004-12-02
申请人： Jian Chen , Tomoharu Tanaka
发明人： Jian Chen , Tomoharu Tanaka
IPC分类号： G11C16/06 , G11C16/04 , G11C29/00 , G06F12/00 , H03M13/00
CPC分类号： G11C11/5635 , G06F11/1068 , G11C11/5621 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C16/349 , G11C2211/5641 , G11C2211/5646
摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.
摘要翻译：在被分成具有存储在每个块中的多页用户数据的存储单元的单独可擦除块的快闪EEPROM系统中，每个块已经承受的擦除周期数的计数被存储在块内的一个位置中，如在仅一页的备用单元中或分布在多页的标题区之间。最初从被擦除的每个块读取包含块循环计数的页面，临时存储循环计数，擦除块，然后将更新的循环计数写回到块位置。然后根据需要将用户数据编程到块的各个页面中。用户数据优选地存储在每个存储器单元存储元件的多于两个状态中，在这种情况下，周期计数可以以加速擦除处理的方式以二进制存储，并且减少写入更新周期的擦除状态的干扰效应计数可以造成。可以与循环计数一起存储从周期计数中计算的纠错码，从而允许验证存储的循环计数。

84. 发明申请

US20070280017A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070280017A1
公开(公告)日：2007-12-06
申请号：US11772271
申请日：2007-07-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

85. 发明授权

US07295469B2 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode 有权
标题翻译：具有可设置为写/擦除禁止模式的ROM块的非易失性半导体存储器件
公开(公告)号：US07295469B2
公开(公告)日：2007-11-13
申请号：US11530340
申请日：2006-09-08
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G11C16/22
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

86. 发明授权

US07286404B2 Non-volatile semiconductor memory adapted to store a multi-valued data in a single memory cell 有权
标题翻译：适用于将多值数据存储在单个存储单元中的非易失性半导体存储器
公开(公告)号：US07286404B2
公开(公告)日：2007-10-23
申请号：US11417185
申请日：2006-05-04
申请人： Tomoharu Tanaka , Jian Chen
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
摘要翻译：非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。

87. 发明授权

US07262455B2 Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system 失效
标题翻译：非易失性半导体存储器件和非易失性半导体存储器系统
公开(公告)号：US07262455B2
公开(公告)日：2007-08-28
申请号：US10823568
申请日：2004-04-14
申请人： Tomoharu Tanaka , Hiroshi Sukegawa
发明人： Tomoharu Tanaka , Hiroshi Sukegawa
IPC分类号： H01L29/76 , H01L23/02
CPC分类号： H01L27/115 , G11C16/0483 , G11C16/08 , H01L2224/48091 , H01L2224/48137 , H01L2224/48464 , H01L2224/49175 , H01L2924/00014 , H01L2924/00
摘要： A nonvolatile semiconductor memory package includes a memory device having a memory cell array including a plurality of nonvolatile semiconductor memory cells, a control portion configured to control the memory device, a network interface connectable to a network, a file management portion connected to the network interface configured to manage a relationship between a data file given from the network and an address of the memory cell array, and a memory interface connected to the file management portion configured to convert a signal given from the network to a signal that is capable of being used at the control portion. The package is wrapped by an insulating material.
摘要翻译：一种非易失性半导体存储器封装，包括具有包括多个非易失性半导体存储单元的存储单元阵列的存储器件，配置为控制存储器件的控制部分，可连接到网络的网络接口，连接到网络接口的文件管理部分被配置为管理从网络给出的数据文件与存储单元阵列的地址之间的关系，以及连接到文件管理部分的存储器接口，被配置为将从网络给出的信号转换为能够被使用的信号在控制部分。包装被绝缘材料包裹。

88. 发明授权

US07139201B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US07139201B2
公开(公告)日：2006-11-21
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

89. 发明申请

US20060206770A1 Non-Volatile Semiconductor Memory With Large Erase Blocks Storing Cycle Counts 有权
标题翻译：具有大擦除块的非易失性半导体存储器存储循环计数
公开(公告)号：US20060206770A1
公开(公告)日：2006-09-14
申请号：US11419696
申请日：2006-05-22
申请人： Jian Chen , Tomoharu Tanaka
发明人： Jian Chen , Tomoharu Tanaka
IPC分类号： G11C29/00
CPC分类号： G11C11/5635 , G06F11/1068 , G11C11/5621 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C16/349 , G11C2211/5641 , G11C2211/5646
摘要： In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause. An error correction code calculated from the cycle count may be stored with it, thereby allowing validation of the stored cycle count.
摘要翻译：在被分成具有存储在每个块中的多页用户数据的存储单元的单独可擦除块的快闪EEPROM系统中，每个块已经承受的擦除周期数的计数被存储在块内的一个位置中，如在仅一页的备用单元中或分布在多页的标题区之间。最初从被擦除的每个块读取包含块循环计数的页面，临时存储循环计数，擦除块，然后将更新的循环计数写回到块位置。然后根据需要将用户数据编程到块的各个页面中。用户数据优选地存储在每个存储器单元存储元件的多于两个状态中，在这种情况下，周期计数可以以加速擦除处理的方式以二进制存储，并且减少写入更新周期的擦除状态的干扰效应计数可以造成。可以与循环计数一起存储从周期计数中计算的纠错码，从而允许验证存储的循环计数。

90. 发明申请

US20060203558A1 Non-volatile semiconductor memory adapted to store a multi-valued data in a single memory cell 有权
标题翻译：适用于将多值数据存储在单个存储单元中的非易失性半导体存储器
公开(公告)号：US20060203558A1
公开(公告)日：2006-09-14
申请号：US11417185
申请日：2006-05-04
申请人： Tomoharu Tanaka , Jian Chen
发明人： Tomoharu Tanaka , Jian Chen
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/34 , G11C16/3418 , G11C16/3427 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
摘要翻译：非易失性半导体存储器件包括电数据可重写非易失性半导体存储单元和用于在存储单元中写入数据的写入电路，写入电路通过提供写入电压Vpgm和写入控制将数据写入存储单元电压VBL到存储器单元，响应于存储单元的第一写入状态的到来改变写入控制电压VBL的值，继续写入存储单元中的数据，并且禁止写入数据的任何操作该存储单元响应于存储单元的第二写入状态的进入而进一步将写入控制电压VBL的值改变为Vdd。

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