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    • 82. 发明授权
    • Polypeptide for a TRP channel family member, TRP-PLIK2, and splice variants
    • 用于TRP通道家族成员的多肽,TRP-PLIK2和剪接变体
    • US07541434B2
    • 2009-06-02
    • US11726234
    • 2007-03-21
    • Ning LeeJian ChenShujian WuHan ChangMichael A. Blanar
    • Ning LeeJian ChenShujian WuHan ChangMichael A. Blanar
    • C07K14/47C12N15/07C12N15/64C12P21/02
    • C07K14/705
    • The present invention provides novel polynucleotides encoding TRP-PLIK2 polypeptides, fragments and homologues thereof. The present invention also provides polynucleotides encoding variants and splice variants of TRP-PLIK2 polypeptides, TRP-PLIK2b, TRP-PLIK2c, and TRP-PLIK2d, respectively. Also provided are vectors, host cells, antibodies, and recombinant and synthetic methods for producing said polypeptides. The invention further relates to diagnostic and therapeutic methods for applying these novel TRP-PLIK2, TRP-PLIK2b, TRP-PLIK2c, and TRP-PLIK2d polypeptides to the diagnosis, treatment, and/or prevention of various diseases and/or disorders related to these polypeptides. The invention further relates to screening methods for identifying agonists and antagonists of the polynucleotides and polypeptides of the present invention.
    • 本发明提供了编码TRP-PLIK2多肽的新型多核苷酸,其片段及其同源物。 本发明还提供分别编码TRP-PLIK2多肽,TRP-PLIK2b,TRP-PLIK2c和TRP-PLIK2d的变体和剪接变体的多核苷酸。 还提供了载体,宿主细胞,抗体以及用于产生所述多肽的重组和合成方法。 本发明还涉及将这些新型TRP-PLIK2,TRP-PLIK2b,TRP-PLIK2c和TRP-PLIK2d多肽应用于诊断,治疗和/或预防与这些相关的各种疾病和/或病症的诊断和治疗方法 多肽。 本发明还涉及用于鉴定本发明的多核苷酸和多肽的激动剂和拮抗剂的筛选方法。
    • 84. 发明授权
    • Modular uninterruptible power supply with loadsharing between modules
    • 模块化不间断电源,模块之间具有负载分担
    • US07492058B2
    • 2009-02-17
    • US11676460
    • 2007-02-19
    • Jian Chen
    • Jian Chen
    • H02J7/00H02J9/00H02J3/00G05D3/12
    • H02J9/062Y10T307/615Y10T307/707
    • In the preferred embodiments, an uninterruptible power supply has multiple UPS modules connected in parallel. Each module has an AC-DC-AC converter and a subcontroller for controlling the operation of the AC-DC-AC converter. A single current sensor senses a total aggregate current flowing from all the modules. Each subcontroller can detect an input voltage, output voltage, and DC bus voltage of each module. Also, each module has unique operating characteristics (e.g., efficiency curve and a responsiveness coefficient K). Operating characteristics data are stored in a memory accessible by the subcontroller. Based on the voltage and current measurements, and the operating characteristics of each module, the subcontrollers perform calculations to determine a DC bus voltage target (unique for each module) that results in each module providing the same output current. Accordingly, only one current sensor is needed, and, consequently, the cost of the UPS device can be reduced.
    • 在优选实施例中,不间断电源具有并联连接的多个UPS模块。 每个模块都有AC-DC-AC转换器和用于控制AC-DC-AC转换器工作的子控制器。 单个电流传感器检测从所有模块流出的总聚合电流。 每个子控制器可以检测每个模块的输入电压,输出电压和直流母线电压。 此外,每个模块具有独特的操作特性(例如效率曲线和响应系数K)。 操作特性数据存储在可由子控制器访问的存储器中。 基于电压和电流测量以及每个模块的工作特性,子控制器执行计算以确定每个模块提供相同输出电流的直流总线电压目标(每个模块唯一)。 因此,仅需要一个电流传感器,因此可以减少UPS装置的成本。
    • 86. 发明授权
    • Gate configuration for nanowire electronic devices
    • 纳米线电子器件的栅极配置
    • US07473943B2
    • 2009-01-06
    • US11233398
    • 2005-09-22
    • Shahriar MostarshedJian ChenFrancisco LeonYaoling PanLinda T. Romano
    • Shahriar MostarshedJian ChenFrancisco LeonYaoling PanLinda T. Romano
    • H01L29/80
    • H01L29/0665B82Y10/00H01L29/0673H01L29/42384H01L29/42392H01L29/775H01L29/785H01L29/78645H01L29/78681H01L29/7869Y10S977/762Y10S977/932Y10S977/938
    • Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.
    • 描述了具有改进的门结构的电子设备的方法,系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面,一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。
    • 87. 发明授权
    • Providing stress uniformity in a semiconductor device
    • 在半导体器件中提供应力均匀性
    • US07473623B2
    • 2009-01-06
    • US11428022
    • 2006-06-30
    • Jian ChenMark W. Michael
    • Jian ChenMark W. Michael
    • H01L21/3205H01L21/4763
    • H01L21/823418H01L21/823814H01L29/7843H01L29/7848
    • A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducing layer is formed over at least a portion of the functional features and the non-functional feature. A device includes a semiconductor layer, a first dummy gate electrode, and a stress-inducing layer. The plurality of transistor gate electrodes is formed above the semiconductor layer. The plurality includes at least a first end gate electrode, a second end gate electrode, and at least one interior gate electrode. The first dummy gate electrode is disposed proximate the first end gate electrode. The stress-inducing layer is disposed over at least a portion of the plurality of transistor gate electrodes and the first dummy gate electrode.
    • 一种方法包括在第一区域中的半导体层上形成多个功能特征。 相邻于功能特征的非功能特征形成在邻近设置在区域周边的功能特征中的至少一个功能特征。 在功能特征和非功能特征的至少一部分上形成应力诱导层。 一种器件包括半导体层,第一伪栅电极和应力诱导层。 多个晶体管栅电极形成在半导体层的上方。 多个至少包括第一端栅极电极,第二端栅极电极和至少一个内部栅极电极。 第一虚拟栅电极设置在第一端栅电极附近。 应力感应层设置在多个晶体管栅极电极和第一虚拟栅电极的至少一部分上。