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    • 83. 发明授权
      US5886553A Semiconductor device having a latch circuit for latching data externally input 失效
    • Semiconductor device having a latch circuit for latching data externally input
    • 具有用于锁存外部输入的数据的锁存电路的半导体装置
    • US5886553A
    • 1999-03-23
    • US79548
    • 1998-05-15
    • Yoshinori Matsui
    • Yoshinori Matsui
    • H03K3/037 , G11C7/22 , G11C8/18 , H03K19/0175 , G11C11/34
    • G11C8/18 , G11C7/22
    • To use a high performance central processing unit (CPU)(e.g., operating with high frequency), a memory system includes a memory cell array having a plurality of word lines connected to memory cells, a latch circuit for receiving and latching a first control signal in response to a first clock signal and for outputting a second control signal, and a decoder for selecting one word line among the word lines in response to an address signal when the decoder receives the second control signal. The latch circuit includes a first latch portion for latching the first control signal during a first cycle of the first clock signal, and a second latch portion for latching the first control signal during a second cycle of the first clock signal.
    • 为了使用高性能中央处理单元（CPU）（例如，以高频操作），存储器系统包括具有连接到存储器单元的多个字线的存储单元阵列，用于接收和锁存第一控制信号的锁存电路 响应于第一时钟信号并输出​​第二控制信号;以及解码器，用于当解码器接收第二控制信号时响应于地址信号在字线中选择一个字线。 锁存电路包括用于在第一时钟信号的第一周期期间锁存第一控制信号的第一锁存部分和用于在第一时钟信号的第二周期期间锁存第一控制信号的第二锁存部分。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 84. 发明授权
      US5815453A Semiconductor memory device having redundant decoder with subtantially constant margin regardless of power voltage level 失效
    • Semiconductor memory device having redundant decoder with subtantially constant margin regardless of power voltage level
    • 半导体存储器件具有冗余解码器，具有小的恒定余量，而与功率电压电平无关
    • US5815453A
    • 1998-09-29
    • US908709
    • 1997-08-08
    • Yoshinori Matsui
    • Yoshinori Matsui
    • G11C11/401 , G11C8/10 , G11C29/00 , G11C29/04 , G11C7/02
    • G11C29/785 , G11C8/10
    • A redundant decoder has a charge line, a plurality of fuse elements connected to the charge line and selectively broken for storing a first address assigned to a defective column group of memory cells and a plurality of switching transistors connected between the fuse elements and a ground line and gated with internal address signals representative of a second address assigned to a column group of memory cells to be accessed, and compares the first address with the second address to see whether or not the defective column group is accessed; when the defective column group is accessed, all of the switching transistors are turned off, and an output circuit generates internal control signals on the basis of the potential level on the charge line so as to replace the defective column group with a redundant column group; when a non-defective column group is accessed, at least one current path is provided from the charge line through the non-broken fuse element and the switching transistor to the ground line, and the output circuit does not produce the internal control signal; and a current mirror circuit is connected between the charge line and the output circuit so as to prevent the output circuit from the resistance of the series of the non-broken fuse element and the associated switching transistor.
    • 冗余解码器具有充电线，连接到充电线的多个熔丝元件，并且选择性地断开以存储分配给存储器单元的缺陷列组的第一地址和连接在熔丝元件与接地线之间的多个开关晶体管 并且选通表示分配给要访问的存储单元的列组的第二地址的内部地址信号，并且将第一地址与第二地址进行比较，以查看是否存取缺陷列组; 当访问有缺陷的列组时，所有开关晶体管都被截止，并且输出电路基于充电线上的电位电平产生内部控制信号，以便用冗余列组代替缺陷列组; 当访问无缺陷列组时，从充电线通过非断开熔丝元件和开关晶体管提供至少一个电流路径到接地线，并且输出电路不产生内部控制信号; 并且电荷镜电路连接在充电线路和输出电路之间，以便防止输出电路与一系列未断开的熔丝元件和相关的开关晶体管的电阻。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 85. 发明授权
      US09152594B2 Semiconductor memory device for high speed reading and writing 有权
    • Semiconductor memory device for high speed reading and writing
    • 半导体存储器件，用于高速读写
    • US09152594B2
    • 2015-10-06
    • US13547799
    • 2012-07-12
    • Nakaba Kaiwa , Yoshinori Matsui
    • Nakaba Kaiwa , Yoshinori Matsui
    • G06F13/36 , G06F13/40
    • G06F13/40 , G06F13/4059
    • A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes external input/output buffers, and bus interface circuits. The bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers. The bus interface circuits are densely arranged between the internal bus and the input/output buffers, so that a width d1 of the area of the plurality of bus interface circuits being arranged is narrower than a width d2 of the area of the external input/output buffers being arranged and a bus width maximum value d3 of the internal bus.
    • 半导体存储器件包括存储单元阵列部分，其包括多个存储单元阵列，外围电路部分和连接多个存储单元阵列和外围电路部分的内部总线。 外围电路部分包括外部输入/输出缓冲器和总线接口电路。 总线接口电路通过内部总线和通过多个外部输入/输出缓冲器以串行方式输入/输出的数据在与存储单元阵列并行输入/输出的数据之间执行转换。 总线接口电路密集地布置在内部总线和输入/输出缓冲器之间，使得布置的多个总线接口电路的区域的宽度d1比外部输入/输出区域的宽度d2窄 布置的缓冲器和内部总线的总线宽度最大值d3。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 90. 发明授权
      US08279692B2 Semiconductor device having hierarchical data line structure and control method thereof 有权
    • Semiconductor device having hierarchical data line structure and control method thereof
    • 具有分层数据线结构及其控制方法的半导体器件
    • US08279692B2
    • 2012-10-02
    • US12910496
    • 2010-10-22
    • Yoshinori Matsui
    • Yoshinori Matsui
    • G11C7/00
    • G11C5/063 , G11C5/025 , G11C11/4097
    • To provide a semiconductor device including switch transistor provided between a sub-data line and a main data line. Upon transferring data, the semiconductor device supplies a potential of a VPP level to a gate electrode of the switch transistor when causing the switch transistor to be a conductive state, and supplies a potential of a VPERI level to the gate electrode when causing the switch transistor to be a non-conductive state. According to the present invention, because a potential of the gate electrode is not decreased to a VSS level when causing the switch transistor to be a non-conductive state, it is possible to reduce a current required to charge and discharge a gate capacitance of the switch transistor. Furthermore, because the VPP level is supplied to the gate electrode when causing the switch transistor to be a conduction state, a level of a signal after transfer never drops down by the amount of the threshold voltage.
    • 提供包括设置在子数据线和主数据线之间的开关晶体管的半导体器件。 在传送数据时，当使开关晶体管成为导通状态时，半导体器件将VPP电平的电位提供给开关晶体管的栅电极，并且当引起开关晶体管时，向栅电极提供VPERI电平的电位 成为非导电状态。 根据本发明，由于当使开关晶体管为非导通状态时，栅电极的电位不降低到VSS电平，所以可以减小对栅极电容的充电和放电所需的电流 开关晶体管。 此外，由于当使开关晶体管成为导通状态时VPP电平被提供给栅电极，所以转移后的信号电平不会下降阈值电压的量。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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