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81. 发明授权

US08867259B2 Method of programming variable resistance nonvolatile memory element 有权
标题翻译：编程可变电阻非易失性存储元件的方法
公开(公告)号：US08867259B2
公开(公告)日：2014-10-21
申请号：US13704649
申请日：2012-08-09
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Shunsaku Muraoka
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh , Shunsaku Muraoka
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C2013/0054 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/56 , G11C2213/79
摘要： A method of programming a variable resistance nonvolatile memory element that removes a defect in a resistance change, ensures an operation widow, and stably sustains a resistance change operation, the method including: applying, when the detect in the resistance change occurs in the variable resistance nonvolatile memory element, a recovery voltage pulse at least once to the variable resistance nonvolatile memory element, the recovery voltage pulse including: a first recovery voltage pulse that has an amplitude greater than amplitudes of a normal high resistance writing voltage pulse and a low resistance writing voltage pulse; and a second recovery voltage pulse that is the low resistance writing voltage pulse following the first recovery voltage pulse.
摘要翻译：一种编程消除电阻变化缺陷的可变电阻非易失性存储元件的方法，确保操作遗ow，并稳定地维持电阻变化操作，该方法包括：当在可变电阻中发生电阻变化的检测时，非易失性存储元件，至少一次到可变电阻非易失性存储元件的恢复电压脉冲，恢复电压脉冲包括：第一恢复电压脉冲，其具有大于正常高电阻写入电压脉冲和低电阻写入的幅度的幅度电压脉冲; 以及第二恢复电压脉冲，其是跟随第一恢复电压脉冲的低电阻写入电压脉冲。

82. 发明授权

US08325508B2 Writing method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储元件和可变电阻非易失性存储器件的写入方法
公开(公告)号：US08325508B2
公开(公告)日：2012-12-04
申请号：US13001905
申请日：2010-06-08
申请人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79
摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).
摘要翻译：提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有最大电阻值。在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻元件从低电阻状态（S52）到高电阻状态（S53）。

83. 发明申请

US20120230085A1 FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：形成可变电阻非易失性存储器元件和可变电阻非易失性存储器件的形成方法
公开(公告)号：US20120230085A1
公开(公告)日：2012-09-13
申请号：US13511275
申请日：2011-09-28
申请人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
发明人： Ken Kawai , Kazuhiko Shimakawa , Koji Katayama , Shunsaku Muraoka
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： In forming, an automatic forming circuit (210) included in a nonvolatile memory device (200) causes a constant current IL to flow in a selected memory cell having a considerably high initial resistance. When the forming generates a filament path in the memory cell and thereby a resistance value is decreased, a potential of a node NBL and a potential of a node Nin are also decreased. If the potentials become lower than that of a reference voltage Vref, an output NO of a difference amplifier (303) for detecting forming success is activated, and a forming success signal Vfp is activated after a delay time depending on the number n of flip flops FF1 to FFn and a clock signal CLK. Thereby, a switch transistor (301) is in a non-conducting state and the forming on a variable resistance element is automatically terminated.
摘要翻译：在形成时，包括在非易失性存储器件（200）中的自动形成电路（210）使得恒定电流IL流过具有相当高的初始电阻的所选择的存储单元。当形成在存储单元中产生细丝通路并由此电阻值减小时，节点NBL的电位和节点Nin的电位也减小。如果电位变得低于参考电压Vref的电位，则激活用于检测成形成功的差分放大器（303）的输出NO，并且根据触发器的数量n在延迟时间之后激活形成成功信号Vfp FF1〜FFn和时钟信号CLK。由此，开关晶体管（301）处于非导通状态，可变电阻元件上的形成自动终止。

84. 发明申请

US20120044749A1 VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE AND METHOD OF FORMING MEMORY CELL 审中-公开
标题翻译：可变电阻非易失性存储器件及形成存储器单元的方法
公开(公告)号：US20120044749A1
公开(公告)日：2012-02-23
申请号：US13266932
申请日：2010-11-02
申请人： Shunsaku Muraoka , Yoshihiko Kanzawa , Takeshi Takagi , Kazuhiko Shimakawa
发明人： Shunsaku Muraoka , Yoshihiko Kanzawa , Takeshi Takagi , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , H01L21/8239 , H01L45/00
CPC分类号： H01L27/2436 , G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/79 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x
摘要翻译：一种可变电阻非易失性存储装置，包括：（i）半导体衬底（301），（ii）具有下电极和上电极（309a，309c）的可变电阻元件（309）和可变电阻层（309b），其电阻值基于各自具有不同极性的电压信号而被可逆地变化并施加在电极（309a，309c）之间，以及（iii）形成在基板上的MOS晶体管（301），其中所述可变电阻层（309b）包括：具有组成MOx和MOy（其中x

85. 发明申请

US20100321982A1 NONVOLATILE STORAGE DEVICE AND METHOD FOR WRITING INTO THE SAME 有权
标题翻译：非易失存储器件及其写入方法
公开(公告)号：US20100321982A1
公开(公告)日：2010-12-23
申请号：US12867392
申请日：2009-12-16
申请人： Takeshi Takagi , Shunsaku Muraoka , Ryotaro Azuma , Kunitoshi Aono
发明人： Takeshi Takagi , Shunsaku Muraoka , Ryotaro Azuma , Kunitoshi Aono
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： H01L27/101 , G11C13/0002 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . . ) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . . ) and bit lines (BL0, BL1, . . . ) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . . ); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . . ); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).
摘要翻译：提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

86. 发明授权

US08395925B2 Forming method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储元件的形成方法和可变电阻非易失性存储器件
公开(公告)号：US08395925B2
公开(公告)日：2013-03-12
申请号：US13001943
申请日：2010-06-04
申请人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0083 , G11C2213/32 , G11C2213/34 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of determining whether or not a current resistance value of the variable resistance element (100) is lower than a resistance value in a high resistance state; and a voltage application step (S36) of applying a voltage pulse having a voltage not exceeding a sum of a forming voltage and a forming margin when the determination is made that the current resistance value is not lower than the resistance value in the high resistance state (No at S35). The determination step (S35) and the voltage application step (S36) are repeated to process all memory cells in a memory array (202) (S34 to S37).
摘要翻译：提供了一种用于对可变电阻元件进行成形以最大化可变电阻元件的操作窗口的最佳形成方法。成形方法用于初始化可变电阻元件（100）。形成方法包括：确定可变电阻元件（100）的当前电阻值是否低于高电阻状态下的电阻值的确定步骤（S35）以及当确定当前电阻值不低于高电阻状态下的电阻值时，施加具有不超过形成电压和形成余量之和的电压的电压脉冲的电压施加步骤（S36）（S35否）。重复确定步骤（S35）和电压施加步骤（S36）以处理存储器阵列（202）中的所有存储器单元（S34至S37）。

87. 发明授权

US08125817B2 Nonvolatile storage device and method for writing into the same 有权
标题翻译：非易失存储装置及其写入方法
公开(公告)号：US08125817B2
公开(公告)日：2012-02-28
申请号：US12867392
申请日：2009-12-16
申请人： Takeshi Takagi , Shunsaku Muraoka , Ryotaro Azuma , Kunitoshi Aono
发明人： Takeshi Takagi , Shunsaku Muraoka , Ryotaro Azuma , Kunitoshi Aono
IPC分类号： G11C11/00 , G11C5/06 , G11C11/34 , G11C5/14 , G11C7/00
CPC分类号： H01L27/101 , G11C13/0002 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1675
摘要： To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, WL1, . . .) and bit lines (BL0, BL1, . . .) and having a resistance value that reversibly changes based on an electrical signal; a row selection circuit-and-driver (103) provided with transistors (103a) each of which applies a predetermined voltage to a corresponding one of the word lines (WL0, WL1, . . .); a column selection circuit-and-driver (104) provided with transistors (104a) each of which applies a predetermined voltage to a corresponding one of the bit lines (BL0, BL1, . . .); and a substrate bias circuit (110) which applies a forward bias voltage to a substrate of such transistors (103a and 104a).
摘要翻译：提供能够实现稳定操作并且包括可变电阻元件的非易失性存储装置（100）。非易失性存储装置（100）包括：存储单元（M111，M112 ...），每个存储单元设置在字线（WL0，WL1 ...）与位线（BL0， BL1，...），并且具有基于电信号可逆地改变的电阻值; 具有晶体管（103a）的行选择电路驱动器（103），每个晶体管将预定电压施加到对应的一个字线（WL0，WL1 ...）; 具有晶体管（104a）的列选择电路驱动器（104），每个晶体管将预定电压施加到相应的位线（BL0，BL1 ...）中; 以及向这种晶体管（103a和104a）的衬底施加正向偏置电压的衬底偏置电路（110）。

88. 发明申请

US20110128776A1 NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING DATA TO NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和将数据写入非易失性存储器件的方法
公开(公告)号：US20110128776A1
公开(公告)日：2011-06-02
申请号：US13056925
申请日：2010-05-14
申请人： Yoshikazu Katoh , Shunsaku Muraoka , Takeshi Takagi
发明人： Yoshikazu Katoh , Shunsaku Muraoka , Takeshi Takagi
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C11/14 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0038 , G11C2013/0073 , G11C2013/009 , G11C2213/15 , G11C2213/34 , G11C2213/79 , G11C2213/82
摘要： A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V1) which is a negative voltage, the resistance variable layer changes to a first resistance state (RH) in such a manner that its resistance value starts increasing when the interelectrode voltage reaches a second voltage (V2) which is a positive voltage which is equal in absolute value to the first voltage, the resistance variable layer changes to the first resistance state in such a manner that the resistance variable layer flows an interelectrode current such that the interelectrode voltage is maintained at a third voltage (V3) higher than the second voltage, when the interelectrode voltage reaches the third voltage, and the resistance variable layer changes to the first resistance state in such a manner that its resistance value stops increasing when the interelectrode current reaches a first current (Ilim) in a state where the interelectrode voltage is not lower than the second voltage and lower than the third voltage, and the load resistor has a characteristic in which when the electric pulse application device outputs an electric pulse of a second application voltage (VP2), a current flowing by applying to the load resistor, a voltage obtained by subtracting the third voltage from the second application voltage, is not higher than a first current value.
摘要翻译：电阻变化层具有电阻变化层变为第二电阻状态（RL）的特性，使得当电极间电压达到作为负电压的第一电压（V1）时，其电阻值停止减小，电阻变化层以这样的方式改变为第一电阻状态（RH），使得当电极间电压达到作为与第一电压的绝对值相等的正电压的第二电压（V2）时，其电阻值开始增加，电阻变化层以这样的方式变化为电阻变化层流动电极间电流，使得当电极间电压达到第三电压时，电极间电压保持在高于第二电压的第三电压（V3），并且电阻变化层以其电阻值停止增加的方式变为第一电阻状态当所述电极间电流在所述电极间电压不低于所述第二电压且低于所述第三电压的状态下达到第一电流（Ilim）时，并且所述负载电阻器具有当所述电脉冲施加装置输出第二施加电压（VP2）的电脉冲，通过施加到负载电阻器流动的电流，从第二施加电压减去第三电压获得的电压不高于第一电流值。

89. 发明申请

US20110110144A1 WRITING METHOD FOR VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
标题翻译：可变电阻非易失性存储器元件的写入方法和可变电阻非易失性存储器件
公开(公告)号：US20110110144A1
公开(公告)日：2011-05-12
申请号：US13001905
申请日：2010-06-08
申请人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
发明人： Ken Kawai , Kazuhiko Shimakawa , Shunsaku Muraoka , Ryotaro Azuma
IPC分类号： G11C11/21
CPC分类号： G11C11/5685 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/56 , G11C2213/79
摘要： A writing method optimum for a variable resistance element which can maximize an operation window of the variable resistance element is provided. The writing method is performed for a variable resistance element that reversibly changes between a high resistance state and a low resistance state depending on a polarity of an applied voltage pulse. The writing method includes a preparation step (S50) and a writing step (S51, S51a, S51b). At the preparation step (S50), resistance values of the variable resistance element are measured by applying voltage pulses of voltages that are gradually increased to the variable resistance element, thereby determining the first voltage V1 for starting high resistance writing and the second voltage V2 having a maximum resistance value. At the HR writing step (S51a), a voltage pulse having a voltage Vp that is equal to or higher than the first voltage V1 and equal to or lower than the second voltage V2 is applied to the variable resistance element, thereby changing the variable resistance element from the low resistance state (S52) to the high resistance state (S53).
摘要翻译：提供了一种最佳可变电阻元件的写入方法，其可以使可变电阻元件的操作窗口最大化。对于根据施加的电压脉冲的极性在高电阻状态和低电阻状态之间可逆地变化的可变电阻元件执行写入方法。写入方法包括准备步骤（S50）和写入步骤（S51，S51a，S51b）。在准备步骤（S50）中，通过向可变电阻元件施加逐渐增加的电压的电压脉冲来测量可变电阻元件的电阻值，从而确定用于开始高电阻写入的第一电压V1和具有最大电阻值。在HR写入步骤（S51a）中，将具有等于或高于第一电压V1并且等于或低于第二电压V2的电压Vp的电压脉冲施加到可变电阻元件，从而改变可变电阻元件从低电阻状态（S52）到高电阻状态（S53）。

90. 发明申请

US20110007553A1 NONVOLATILE STORAGE DEVICE AND METHOD FOR WRITING INTO MEMORY CELL OF THE SAME 有权
标题翻译：非易失存储器件和用于写入其中的存储器单元的方法
公开(公告)号：US20110007553A1
公开(公告)日：2011-01-13
申请号：US12865193
申请日：2009-10-16
申请人： Takeshi Takagi , Shunsaku Muraoka , Mitsuteru Iijima , Ken Kawai , Kazuhiko Shimakawa
发明人： Takeshi Takagi , Shunsaku Muraoka , Mitsuteru Iijima , Ken Kawai , Kazuhiko Shimakawa
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0083 , G11C2013/009 , G11C2213/32 , G11C2213/56 , G11C2213/79
摘要： Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.
摘要翻译：提供一种能够在不增加包含在每个存储单元中的选择晶体管的尺寸的情况下稳定地工作的非易失性存储装置（200）。非易失性存储装置（200）包括：具有第一导电型的P型阱（301a）的半导体基板（301）存储单元阵列（202），其包括存储单元（M11）等，每个存储单元包括形成在半导体衬底（301）上并串联连接的可变电阻元件（R11）和晶体管（N11）; 以及衬底偏置电路（220），当用于写入的电压脉冲为写入电压脉冲时，向P型阱（301a）施加相对于晶体管（N11）的源极和漏极的正向偏置电压应用于所选择的存储单元（M11）等中包含的可变电阻元件（R11）。

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