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81. 发明申请

US20110033711A1 RESIN-METAL BONDED ARTICLE AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：树脂金属粘合物及其制造方法
公开(公告)号：US20110033711A1
公开(公告)日：2011-02-10
申请号：US12735062
申请日：2008-12-15
申请人： Masumi Kuroyama , Kazuo Kato , Tomonori Ishikawa , Yaeko Sasaki , Setsuko Sato , Masayuki Nakamura , Shuhei Miura
发明人： Masumi Kuroyama , Kazuo Kato , Tomonori Ishikawa , Yaeko Sasaki , Setsuko Sato , Masayuki Nakamura , Shuhei Miura
IPC分类号： B32B15/08 , B32B27/06 , B29C70/68
CPC分类号： B29C45/14311 , B29K2067/006 , B29K2081/04 , B29K2705/00 , Y10T156/1089 , Y10T428/31533 , Y10T428/31678 , Y10T428/31681 , Y10T428/31786
摘要： Disclosed is a resin-metal bonded article which is improved in adhesion between a copper component and a PPS or PBT resin. Also disclosed is a method for producing such a resin-metal bonded article. The resin-metal bonded article is obtained by bonding the resin component onto the surface of the copper component through a copper component bonding surface where there is copper oxide in the following range: 10%≦Cu2O/(Cu2O+CuO)≦75%. Preferably, this resin-metal bonded article further contains a triazine thiol derivative in the resin-component-side bonding surface of the copper component.
摘要翻译：公开了一种改善了铜成分和PPS或PBT树脂之间的粘合性的树脂 - 金属接合体。还公开了一种用于制造这种树脂 - 金属粘合制品的方法。树脂金属接合体是通过将铜氧化物的铜成分接合面与铜成分的表面接合而得到的，其中，氧化铜的含量为10％以下; Cu 2 O /（Cu 2 O + CuO）％。优选地，该树脂金属粘合体在铜成分的树脂成分侧接合面中还含有三嗪硫醇衍生物。

82. 发明授权

US07796456B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07796456B2
公开(公告)日：2010-09-14
申请号：US11616755
申请日：2006-12-27
申请人： Chiaki Dono , Yasuji Koshikawa , Masayuki Nakamura
发明人： Chiaki Dono , Yasuji Koshikawa , Masayuki Nakamura
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/785 , G11C2229/763
摘要： A semiconductor device is configured to prevent misprogramming of fuse circuits therein. The semiconductor device includes the following elements. A group of fuse element circuits 911 is configured to store a first data defining the circuit configuration. A fuse element circuit 913 is configured to store a second data representing inhibition of programming the group of fuse element circuits. A control logic circuit 140 is configured to program the first and the second data on the fuse element circuits. An AND gate circuit 914 is configured to inhibit the control logic circuit 140 from programming the group of fuse element circuits 911 on condition that the fuse element circuit 913 has been programmed.
摘要翻译：半导体器件被配置为防止其中熔丝电路的错误编程。半导体器件包括以下元件。一组熔丝元件电路911被配置为存储限定电路配置的第一数据。熔丝元件电路913被配置为存储表示对熔丝元件电路组编程的禁止的第二数据。控制逻辑电路140被配置为对熔丝元件电路上的第一和第二数据进行编程。 AND门电路914被配置为在熔丝元件电路913被编程的条件下禁止控制逻辑电路140对熔丝元件电路组911进行编程。

83. 发明授权

US07772931B2 Oscillator and a tuning method of a loop bandwidth of a phase-locked-loop 有权
标题翻译：振荡器和锁相环的环路带宽调谐方法
公开(公告)号：US07772931B2
公开(公告)日：2010-08-10
申请号：US12135202
申请日：2008-06-08
申请人： Masayuki Nakamura
发明人： Masayuki Nakamura
IPC分类号： H03L7/085 , H03L7/093 , H03L7/18
CPC分类号： H03L7/093 , H03H7/0153 , H03L7/0898 , H03L7/099
摘要： There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.
摘要翻译：提供了一种振荡器，包括：参考信号发生器，其产生具有参考频率的参考信号; 相位比较器，根据参考信号和反馈信号之间的相位差输出电压; 接收从相位比较器输出的电压的环路滤波器，并通过外部控制信号增益调节从相位比较器输出的电压; 电压控制振荡器，其根据经过环路滤波器增益调整的经调整的信号以频率振荡输出信号; 以及分频器，将从分频输出信号得到的分频信号反馈到相位比较器作为反馈信号。

84. 发明申请

US20090322759A1 LINE PLOTTING METHOD 有权
标题翻译：线绘图法
公开(公告)号：US20090322759A1
公开(公告)日：2009-12-31
申请号：US12428212
申请日：2009-04-22
申请人： Kouji Nishikawa , Makato Adachi , Masayuki Nakamura , Motonobu Mamiya , Kae Yamashita
发明人： Kouji Nishikawa , Makato Adachi , Masayuki Nakamura , Motonobu Mamiya , Kae Yamashita
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： A line plotting method for plotting lines whose coordinates are given on a display screen on which pixels are arranged according to a prescribed rule, the method includes correcting coordinates at the end point of a line on the basis of which the end point is a starting point or an ending point or whether the end point is inside a prescribed frame determining whether a direction from a starting point of a line after correction toward its ending point horizontally or vertically is the same as a direction from a starting point before correction of a line toward its ending point determining whether integer values of the coordinates of starting and ending points after correction are the same when directions from starting points after and before correction of a line toward their ending points are not matched.
摘要翻译：一种线绘制方法，用于绘制在根据规定的规则排列像素的显示屏上给出其坐标的线，该方法包括校正终点处的起点处的线的终点处的坐标或者终点是否在规定的帧内，确定从校正后的线的起点到水平或垂直的终点的方向是否与从线的校正前的起点的方向相同其终点确定校正后的开始点和结束点的坐标的整数值是否相同，当从线路朝向其终点的校正之前和之后的起始点的方向不匹配时。

85. 发明授权

US07633833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07633833B2
公开(公告)日：2009-12-15
申请号：US12028788
申请日：2008-02-09
申请人： Riichiro Takemura , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
发明人： Riichiro Takemura , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译：根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

86. 发明申请

US20090002048A1 Reference voltage generating circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20090002048A1
公开(公告)日：2009-01-01
申请号：US12230489
申请日：2008-08-29
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： H03L5/00
CPC分类号： G05F3/30
摘要： Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1. The reference voltage generating circuit outputs a voltage corresponding to the sum of a voltage generated across both ends of the resistor R1 and a base-to-emitter voltage VBE3 of the transistor Q3.
摘要翻译：公开了一种参考电压产生电路，其包括电阻器R0，R0和R3，差分放大器A1和晶体管Q1，Q2和Q3。晶体管Q1和Q2的集电极连接到差分放大器的差分输入端，而R0，R0和R3的一端共同连接到差分放大器A1的输出端。两个电阻R0的另一端共同连接到晶体管Q1和Q2的集电极，而电阻器R1的另一端连接到晶体管Q3的集电极和基极，晶体管Q3的基极连接到晶体管Q1和Q2的基极。晶体管Q1和Q2的发射极尺寸比设定为1：N。导致大致等于晶体管Q1或Q2的集电极电流的值的电流和大于先前电流的正温度系数的电流流过电阻器R1。参考电压产生电路输出与电阻器R1两端产生的电压和晶体管Q3的基极 - 发射极电压VBE3之和的和相对应的电压。

87. 发明申请

US20080239865A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080239865A1
公开(公告)日：2008-10-02
申请号：US12028788
申请日：2008-02-09
申请人： Riichiro TAKEMURA , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
发明人： Riichiro TAKEMURA , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译：根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

88. 发明授权

US07413660B2 Single pass method and apparatus for separating a target molecule from a liquid mixture 有权
标题翻译：用于从液体混合物中分离靶分子的单程方法和装置
公开(公告)号：US07413660B2
公开(公告)日：2008-08-19
申请号：US11241524
申请日：2005-09-30
申请人： Kelly J. Gibbens , Masayuki Nakamura , Kannan Seshadri , Andrew W. Rabins , Larry J. Carson , Robert T. Fitzsimons, Jr.
发明人： Kelly J. Gibbens , Masayuki Nakamura , Kannan Seshadri , Andrew W. Rabins , Larry J. Carson , Robert T. Fitzsimons, Jr.
IPC分类号： B01D15/08
CPC分类号： B01D15/1828 , B01D15/1842
摘要： A single pass simulated moving bed apparatus and methods are described for continuously separating a target molecule from a liquid mixture, using a simulated moving bed system. The simulated moving bed system includes a plurality of filter cartridge modules in serial fluid communication. Each filter cartridge module includes a volume of stationary phase particulates adjacent a porous substrate layer. The volume of stationary phase particulates has a bed height of less than 1 centimeter.
摘要翻译：描述了使用模拟移动床系统连续分离目标分子与液体混合物的单程模拟移动床装置和方法。模拟移动床系统包括串联流体连通的多个滤芯模块。每个过滤器滤芯模块包括邻近多孔基底层的体积的固定相颗粒。固定相颗粒的体积具有小于1厘米的床高度。

89. 发明申请

US20080017904A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080017904A1
公开(公告)日：2008-01-24
申请号：US11773990
申请日：2007-07-06
申请人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
发明人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , G11C7/18 , G11C11/404 , G11C11/4097 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.
摘要翻译：提供了能够实现降低功耗，高速运行和高可靠性的DRAM。构成DRAM的存储单元晶体管的栅电极由n型多晶硅膜和堆叠在其上的W（钨）膜构成。为了延长存储单元晶体管的有效沟道长度，多晶硅膜的一部分嵌入在硅衬底中形成的沟槽中。多晶硅膜的另一部分位于沟槽上方，其上表面位于硅衬底的表面上方（p型阱）。因此，确保W膜与源极和漏极（n型半导体区域）之间的距离。

90. 发明申请

US20070007617A1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070007617A1
公开(公告)日：2007-01-11
申请号：US11480909
申请日：2006-07-06
申请人： Masayuki Nakamura , Satoshi Ishikura , Takayuki Yamada
发明人： Masayuki Nakamura , Satoshi Ishikura , Takayuki Yamada
IPC分类号： H01L29/00 , G11C11/00
CPC分类号： H01L27/11
摘要： An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor and the substrate contact region. The dummy gate electrode is electrically connected to a P-type impurity region of the substrate contact region.
摘要翻译：形成隔离绝缘膜，使得第一存取晶体管和基板接触区域的有源区域可以在平面图中彼此一体化。在第一存取晶体管的有源区和衬底接触区之间的半导体衬底上形成伪栅电极。虚拟栅电极与衬底接触区域的P型杂质区电连接。

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