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81. 发明申请

US20120241913A1 MICROELECTRONIC SUBSTRATE HAVING REMOVABLE EDGE EXTENSION ELEMENT 有权
标题翻译：具有可移除边缘延伸元件的微电子基板
公开(公告)号：US20120241913A1
公开(公告)日：2012-09-27
申请号：US13490239
申请日：2012-06-06
申请人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
发明人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
IPC分类号： H01L29/06
CPC分类号： G03F7/70691 , G03F7/70341 , G03F7/70808
摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.
摘要翻译：提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。前表面是物品的主要表面。具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。以这种方式，形成连续表面，其包括边缘延伸元件的前表面，该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸，连续表面基本上共平面且平坦，周缘连接到内边缘。

82. 发明申请

US20120175775A1 INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS 失效
标题翻译：集成电路与电气障碍
公开(公告)号：US20120175775A1
公开(公告)日：2012-07-12
申请号：US13424651
申请日：2012-03-20
申请人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Takeshi Nogami , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76847 , H01L21/76852 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.
摘要翻译：包括电迁移屏障的集成电路包括线，该线包括第一导电材料，该线还包括由一个或多个电迁移屏障隔开的多个线段，其中所述一个或多个电迁移屏障包括隔离的第二导电材料线路各部分的电迁移效应。

83. 发明申请

US20120142182A1 MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION 有权
标题翻译：通过选择性沉积的微电子结构
公开(公告)号：US20120142182A1
公开(公告)日：2012-06-07
申请号：US13372058
申请日：2012-02-13
申请人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/28
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795 , H01L29/78645
摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
摘要翻译： finFET结构包括位于衬底上的半导体鳍片。栅电极穿过半导体鳍片。栅电极具有邻接其侧壁的间隔层。间隔层不完全覆盖半导体鳍片的侧壁。栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖半导体鳍片可以使用侧向生长方法制造其它微电子结构。

84. 发明授权

US08183159B2 Device component forming method with a trim step prior to sidewall image transfer (SIT) processing 有权
标题翻译：在侧壁图像转印（SIT）处理之前具有修整步骤的装置部件形成方法
公开(公告)号：US08183159B2
公开(公告)日：2012-05-22
申请号：US12062618
申请日：2008-04-04
申请人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Quyang
发明人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Quyang
IPC分类号： H01L21/311
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：本文公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，其需要将修剪掩模对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

85. 发明申请

US20120068346A1 STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME 有权
标题翻译：用于纳米尺度金属化的结构及其制造方法
公开(公告)号：US20120068346A1
公开(公告)日：2012-03-22
申请号：US12885665
申请日：2010-09-20
申请人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
发明人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53266 , H01L21/32139 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.
摘要翻译：为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

86. 发明申请

US20120037962A1 SEMICONDUCTOR STRUCTURE HAVING A CONTACT-LEVEL AIR GAP WITHIN THE INTERLAYER DIELECTRICS ABOVE A SEMICONDUCTOR DEVICE AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE USING A SELF-ASSEMBLY APPROACH 有权
标题翻译：在半导体器件之前的中间层电介质中具有接触层空气隙的半导体结构和使用自组装方法形成半导体结构的方法
公开(公告)号：US20120037962A1
公开(公告)日：2012-02-16
申请号：US12854352
申请日：2010-08-11
申请人： Gregory Breyta , David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
发明人： Gregory Breyta , David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
IPC分类号： H01L23/48 , H01L21/768 , H01L29/78
CPC分类号： H01L21/7682 , H01L21/31144 , H01L23/4821 , H01L23/485 , H01L23/5222 , H01L23/5329 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.
摘要翻译：公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。还公开了使用自组装方法形成这种半导体结构的方法的实施例。

87. 发明申请

US20110193230A1 FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES 失效
标题翻译：形成有保护金属线的空气隙
公开(公告)号：US20110193230A1
公开(公告)日：2011-08-11
申请号：US12700792
申请日：2010-02-05
申请人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
发明人： Takeshi Nogami , Shyng-Tsong Chen , David V. Horak , Son V. Nguyen , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L24/80 , H01L21/0337 , H01L21/31144 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L23/53295
摘要： A method is provided for fabricating a microelectronic element having an air gap in a dielectric layer thereof. A dielectric cap layer can be formed which has a first portion overlying surfaces of metal lines, the first portion extending a first height above a height of a surface of the dielectric layer and a second portion overlying the dielectric layer surface and extending a second height above the height of the surface of the dielectric layer, the second height being greater than the first height. After forming the cap layer, a mask can be formed over the cap layer. The mask can have a multiplicity of randomly disposed holes. Each hole may expose a surface of only the second portion of the cap layer which has the greater height. The mask may fully cover a surface of the first portion of the cap layer having the lower height. Subsequently, an etchant can be directed towards the first and second portions of the cap layer to form holes in the cap layer aligned with the holes in the mask. Material can be removed from the dielectric layer where exposed to the etchant by the holes in the cap layer. At such time, the mask can protect the first portion of the cap layer and the metal lines from being attacked by the etchant.
摘要翻译：提供了一种用于制造其电介质层中具有气隙的微电子元件的方法。可以形成介电盖层，其具有覆盖金属线表面的第一部分，第一部分在电介质层的表面的高度之上延伸第一高度，以及覆盖介电层表面的第二部分，并且延伸第二高度电介质层的表面的高度，第二高度大于第一高度。在形成盖层之后，可以在盖层之上形成掩模。掩模可以具有多个随机布置的孔。每个孔可以暴露仅具有较大高度的盖层的第二部分的表面。掩模可以完全覆盖具有较低高度的盖层的第一部分的表面。随后，可以将蚀刻剂引导到盖层的第一和第二部分，以在盖层中形成与掩模中的孔对准的孔。可以通过盖层中的孔从暴露于蚀刻剂的介电层去除材料。此时，掩模可以保护盖层的第一部分和金属线不被蚀刻剂侵蚀。

88. 发明授权

US07943480B2 Sub-lithographic dimensioned air gap formation and related structure 有权
标题翻译：亚光刻尺寸气隙形成及相关结构
公开(公告)号：US07943480B2
公开(公告)日：2011-05-17
申请号：US12029800
申请日：2008-02-12
申请人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
发明人： Daniel C. Edelstein , Nicholas C. M. Fuller , David V. Horak , Elbert E. Huang , Wai-Kin Li , Anthony D. Lisi , Satyanarayana V. Nitta , Shom Ponoth
IPC分类号： H01L23/00
CPC分类号： H01L21/7682 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.
摘要翻译：公开了亚光刻尺寸气隙形成和相关结构。在一个实施例中，一种方法包括在衬底上形成包括互连的介质层; 在电介质层上沉积盖层; 在所述盖层上沉积光致抗蚀剂; 图案化光致抗蚀剂以包括最多部分地覆盖互连的第一沟槽图案; 在所述第一沟槽图案内形成间隔物以形成具有亚光刻尺寸的第二沟槽图案; 将所述第二沟槽图案转移到所述覆盖层中并进入所述互连之间的所述介电层; 并且通过夹住介电层中的沟槽而沉积另一介质层以形成气隙。

89. 发明授权

US07928420B2 Phase change tip storage cell 有权
标题翻译：相变尖端存储单元
公开(公告)号：US07928420B2
公开(公告)日：2011-04-19
申请号：US10732580
申请日：2003-12-10
申请人： David V. Horak , Chung H. Lam , Hon-Sum P. Wong
发明人： David V. Horak , Chung H. Lam , Hon-Sum P. Wong
IPC分类号： H01L21/00 , H01L21/06
CPC分类号： H01L45/06 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1691
摘要： A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.
摘要翻译：具有一个或多个存储单元的存储单元，集成电路（IC）芯片，其可以是存储单元阵列，以及形成存储单元和IC的方法。每个存储单元包括触针，其尖端是相变材料。相变尖端可以夹在电极和导电材料之间，例如氮化钛（TiN），氮化钽（TaN）或n型半导体。相变层可以是硫族化物，特别是锗（Ge），锑（Sb），碲（Te）（GST）层。

90. 发明授权

US07855428B2 Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer 有权
标题翻译：在浅沟槽隔离结构和掩埋氧化物层之间的界面处的导电衬垫
公开(公告)号：US07855428B2
公开(公告)日：2010-12-21
申请号：US12115699
申请日：2008-05-06
申请人： Robert H. Dennard , Mark C. Hakey , David V. Horak , Sanjay Mehta
发明人： Robert H. Dennard , Mark C. Hakey , David V. Horak , Sanjay Mehta
IPC分类号： H01L21/76
CPC分类号： H01L21/76283
摘要： The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SOI. A dielectric liner is formed at an interface of the SOI within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.
摘要翻译：本发明涉及一种设计结构，更具体地，涉及一种用于辐射硬总剂量免疫的导电衬垫的设计结构及其结构。该结构包括至少一个具有氧化物材料并在SOI中形成的浅沟槽隔离结构。在所述至少一个浅沟槽隔离结构内的SOI的界面处形成电介质衬垫。在所述至少一个浅沟槽隔离结构中以及所述电介质衬垫和所述氧化物材料之间形成金属或金属合金层。

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