专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US06754782B2 Decentralized global coherency management in a multi-node computer system 有权
标题翻译：在多节点计算机系统中进行分散的全局一致性管理
公开(公告)号：US06754782B2
公开(公告)日：2004-06-22
申请号：US09885994
申请日：2001-06-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0817
摘要： A non-uniform memory access (NUMA) computer system includes a first node and a second node coupled by a node interconnect. The second node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, and a controller coupled to the local interconnect. In response to snooping an operation from the first node issued on the local interconnect by the node controller, the controller signals acceptance of responsibility for coherency management activities related to the operation in the second node, performs coherency management activities in the second node required by the operation, and thereafter provides notification of performance of the coherency management activities. To promote efficient utilization of queues within the node controller, the node controller preferably allocates a queue to the operation in response to receipt of the operation from the node interconnect and then deallocates the queue in response to transferring responsibility for coherency management activities to the controller.
摘要翻译：非均匀存储器访问（NUMA）计算机系统包括通过节点互连耦合的第一节点和第二节点。第二节点包括本地互连，耦合在本地互连和节点互连之间的节点控制器以及耦合到本地互连的控制器。响应于通过节点控制器窥探在本地互连上发出的第一节点的操作，控制器指示接受与第二节点中的操作有关的一致性管理活动的责任，在第二节点执行所需的第二节点中的一致性管理活动操作，然后提供一致性管理活动的执行通知。为了促进节点控制器内的队列的有效利用，节点控制器优选地响应于从节点互连接收到该操作而将该队列分配给该操作，然后响应于向控制器传送一致性管理活动的责任而释放该队列。

82. 发明授权

US06658538B2 Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control 有权
标题翻译：具有包括节点特定数据存储和一致性控制的页表的非均匀存储器访问（NUMA）数据处理系统
公开(公告)号：US06658538B2
公开(公告)日：2003-12-02
申请号：US09885997
申请日：2001-06-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0888 , G06F12/0813
摘要： A non-uniform memory access (NUMA) data processing system includes a plurality of nodes coupled to a node interconnect. The plurality of nodes contain a plurality of processing units and at least one system memory having a table (e.g., a page table) resident therein. The table includes at least one entry for translating a group of non-physical addresses to physical addresses that individually specifies control information pertaining to the group of non-physical addresses for each of the plurality of nodes. The control information may include one or more data storage control fields, which may include a plurality of write through indicators that are each associated with a respective one of the plurality of nodes. When a write through indicator is set, processing units in the associated node write modified data back to system memory in a home node rather than caching the data. The control information may further include a data storage control field comprising a plurality of non-cacheable indicators that are each associated with a respective one of the plurality of nodes. When a non-cacheable indicator is set, processing units in the associated node are instructed to not cache data associated with non-physical addresses within the group translated by reference to the table entry. The control information may also include coherency control information that individually indicates for each node whether or not inter-node coherency for data associated with the table entry will be maintained with software support.
摘要翻译：非均匀存储器访问（NUMA）数据处理系统包括耦合到节点互连的多个节点。多个节点包含多个处理单元和至少一个具有驻留在其中的表（例如，页表）的系统存储器。该表包括用于将一组非物理地址转换为物理地址的至少一个条目，该物理地址分别指定与多个节点中的每一个节点的非物理地址组有关的控制信息。控制信息可以包括一个或多个数据存储控制字段，其可以包括多个写入指示符，每个写入指示符与多个节点中的相应一个节点相关联。当设置写入指示符时，相关节点中的处理单元将修改的数据写回到家庭节点中的系统存储器，而不是缓存数据。控制信息还可以包括数据存储控制字段，该数据存储控制字段包括多个不可缓存的指示符，每个指示符与多个节点中的相应一个相关联。当设置不可缓存的指示符时，指示相关联的节点中的处理单元不缓存通过参考表条目转换的组内与非物理地址相关联的数据。控制信息还可以包括对于每个节点单独指示用于与表条目相关联的数据的节点间一致性的一致性控制信息将用软件支持来维护。

83. 发明授权

US06654857B2 Non-uniform memory access (NUMA) computer system having distributed global coherency management 失效
公开(公告)号：US06654857B2
公开(公告)日：2003-11-25
申请号：US09885991
申请日：2001-06-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0813
摘要： A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, and a memory controller coupled to the local interconnect and the home system memory. In response to receipt of a data request from the remote node, the memory controller transmits requested data from the home system memory to the remote node and, in a separate transfer, conveys responsibility for global coherency management for the requested data from the home node to the remote node. By decoupling responsibility for global coherency management from delivery of the requested data in this manner, the memory controller queue allocated to the data request can be deallocated earlier, thus improving performance.

84. 发明授权

US07058767B2 Adaptive memory access speculation 失效
标题翻译：自适应内存访问推测
公开(公告)号：US07058767B2
公开(公告)日：2006-06-06
申请号：US10425400
申请日：2003-04-28
申请人： John Steven Dodson , James Stephen Fields, Jr. , Sanjeev Ghai , Jeffrey Adam Stuecheli
发明人： John Steven Dodson , James Stephen Fields, Jr. , Sanjeev Ghai , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G06F12/0215
摘要： A method and system for speculatively pre-fetching data from a memory. A memory controller on a data bus “snoops” data requests put on the data bus by a bus control logic. Based on information in the header of the data request, such as transaction type, tag, transaction size, etc., a speculative pre-fetch is made to read data from the memory associated with the memory controller. If the speculative fetch turns out to be correct, then the memory controller makes an assumption that the pre-fetch was too conservative (non-speculative), and a pre-fetch for a next data request is performed at an earlier more speculative time. If the speculative fetch turns out to be incorrect, then the memory controller makes an assumption that the pre-fetch was too speculative (made early), and a pre-fetch for a next data request is performed at a later less speculative time.
摘要翻译：用于从存储器中推测性地预取数据的方法和系统。数据总线上的存储器控制器通过总线控制逻辑“窥探”数据总线上的数据请求。基于诸如事务类型，标签，事务大小等的数据请求的报头中的信息，进行推测性预取以从与存储器控制器相关联的存储器读取数据。如果推测性提取结果是正确的，那么内存控制器假定预取过于保守（非推测性），并且在更早的更多投机时间下执行下一个数据请求的预取。如果推测性提取结果不正确，则存储器控制器假定预取太过于推测（提前），并且在稍后较少的推测时间执行下一个数据请求的预取。

85. 发明授权

US06901485B2 Memory directory management in a multi-node computer system 失效
标题翻译：多节点计算机系统中的内存目录管理
公开(公告)号：US06901485B2
公开(公告)日：2005-05-31
申请号：US09886000
申请日：2001-06-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F2212/2542
摘要： A computer system includes a home node and one or more remote nodes coupled by a node interconnect. The home node includes a local interconnect, a node controller coupled between the local interconnect and the node interconnect, a home system memory, a memory directory including a plurality of entries, and a memory controller coupled to the local interconnect, the home system memory and the memory directory. The memory directory includes a plurality of entries that each provide an indication of whether or not an associated data granule in the home system memory has a corresponding cache line held in at least one remote node. The memory controller includes demand invalidation circuitry that, responsive to a data request for a requested data granule in the home system memory, reads an associated entry in the memory directory and issues an invalidating command to at least one remote node holding a cache line corresponding to the requested data granule. In addition, the memory controller includes directory scrubbing logic that, independently of any data request, periodically reads entries in the memory directory and, responsive to an entry indicating at least one remote node holds a cache line corresponding to the associated data granule, issues a flush query to the at least one remote node to request deallocation of the cache line corresponding to the associated data granule.
摘要翻译：计算机系统包括家庭节点和通过节点互连耦合的一个或多个远程节点。家庭节点包括本地互连，耦合在本地互连和节点互连之间的节点控制器，家庭系统存储器，包括多个条目的存储器目录，以及耦合到本地互连的存储器控制器，家庭系统存储器和内存目录。存储器目录包括多个条目，每个条目提供关于家庭系统存储器中的相关联的数据粒子是否具有保存在至少一个远程节点中的相应高速缓存行的指示。存储器控制器包括：请求无效电路，响应于家庭系统存储器中的所请求的数据粒子的数据请求，读取存储器目录中的相关联的条目并且向至少一个远程节点发出无效命令，该远程节点保存对应于请求的数据颗粒。此外，存储器控制器包括目录擦除逻辑，其独立于任何数据请求，周期性地读取存储器目录中的条目，并且响应于指示至少一个远程节点保存与相关联的数据粒子对应的高速缓存行的条目，发出一个对至少一个远程节点进行刷新查询以请求对应于相关联的数据粒子的高速缓存行的释放。

86. 发明授权

US06615322B2 Two-stage request protocol for accessing remote memory data in a NUMA data processing system 失效
公开(公告)号：US06615322B2
公开(公告)日：2003-09-02
申请号：US09885996
申请日：2001-06-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0813
摘要： A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node having a home system memory. The remote node includes a local interconnect, a processing unit and at least one cache coupled to the local interconnect, and a node controller coupled between the local interconnect and the node interconnect. The processing unit first issues, on the local interconnect, a read-type request targeting data resident in the home system memory with a flag in the read-type request set to a first state to indicate only local servicing of the read-type request. In response to inability to service the read-type request locally in the remote node, the processing unit reissues the read-type request with the flag set to a second state to instruct the node controller to transmit the read-type request to the home node. The node controller, which includes a plurality of queues, preferably does not queue the read-type request until receipt of the reissued read-type request with the flag set to the second state.

87. 发明申请

US20130117513A1 MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH LATENCY MEMORY OPERATIONS 有权
标题翻译：用于减少高级存储器操作影响的存储器队列处理技术
公开(公告)号：US20130117513A1
公开(公告)日：2013-05-09
申请号：US13290702
申请日：2011-11-07
申请人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/14
CPC分类号： G06F13/1626 , G06F13/16
摘要： Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.
摘要翻译：用于处理存储器访问排队的技术防止传递过多的请求，这些请求涉及存储器的区域，这些存储器受到诸如存储器刷新操作，存储器擦除或内部总线校准事件的高等待时间存储器操作到存储器的重新排序队列控制器。存储器控制器包括用于存储未决存储器访问请求的队列，用于接收请求的重新排序队列，以及实现队列控制器的控制逻辑，该队列控制器确定接收到的请求和正在进行的高延迟存储器操作之间是否存在冲突。如果存在冲突，则将请求转发到重新排序队列可能被直接拒绝，或者可能使用与高等待时间操作相冲突的现有排队操作的计数来确定新请求的队列是否将超过阈值此类操作的数量。

88. 发明授权

US06662216B1 Fixed bus tags for SMP buses 失效
标题翻译：用于SMP总线的固定总线标签
公开(公告)号：US06662216B1
公开(公告)日：2003-12-09
申请号：US08839478
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明的第一方面，提供一种数据处理系统，其包括多个设备耦合到的通信网络。多个设备中的第一个包括多个请求者（或队列），每个请求者（或队列）被永久地分配多个唯一标签中的相应的一个。响应于第一设备内的请求者的通信请求，分配给请求者的标签与所请求的通信事务一起在通信网络上发送。根据本发明的第二方面，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

89. 发明授权

US06507880B1 Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens 失效
标题翻译：总线协议，总线主机和总线监听器，用于执行使用多个令牌的全局操作
公开(公告)号：US06507880B1
公开(公告)日：2003-01-14
申请号：US09435927
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the global operation and identifies the global operation to be processed with the token, if granted. Bus snoopers contain a number of snooper queues for global operations equal to the number of global operation tokens employed within the multiprocessor system. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. Before completing the operation, the snooper watches for a combined response with a token number acknowledging either the combined request or a subsequent token request from the same processor, which indicates that the originating bus master has been granted a token for completing a global operation. Otherwise, a combined response acknowledging an operation request containing the token number implies release of the granted token.
摘要翻译：响应于启动全局操作的需要，多处理器系统内的总线主机在耦合到总线主机的总线上发出组合的令牌和操作请求。组合的令牌和操作请求请求完成全局操作所需的多个令牌中的一个令牌，并且如果被授权则标识要用令牌处理的全局操作。总线侦听器包含多个用于全局操作的侦听队列，等于在多处理器系统中使用的全局操作令牌的数量。一旦检测到组合的令牌和操作请求，总线侦听器开始推测性地处理该操作，如果该侦听器尚未忙。在完成操作之前，窥探者使用令牌号来识别来自同一处理器的组合请求或后续令牌请求的组合响应，其指示始发总线主机已经被授予用于完成全局操作的令牌。否则，确认包含令牌号的操作请求的组合响应意味着释放所授予的令牌。

90. 发明授权

US06502168B1 Cache having virtual cache controller queues 失效
标题翻译：缓存具有虚拟缓存控制器队列
公开(公告)号：US06502168B1
公开(公告)日：2002-12-31
申请号：US09404028
申请日：1999-09-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式