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81. 发明申请

US20110185254A1 ERROR DETECTION AND CORRECTION SCHEME FOR A MEMORY DEVICE 有权
标题翻译：用于存储器件的错误检测和校正方案
公开(公告)号：US20110185254A1
公开(公告)日：2011-07-28
申请号：US13080299
申请日：2011-04-05
申请人： William H. Radke , Shuba Swaminathan , Brady L. Keays
发明人： William H. Radke , Shuba Swaminathan , Brady L. Keays
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H03M13/096 , G06F11/1008
摘要： Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.
摘要翻译：从存储器阵列中读取数据。在存储在数据缓冲器中之前，并行地操作汉明码检测操作和里德 - 所罗门码检测操作，以确定数据字是否具有任何错误。并行检测操作的结果被传送到控制器电路。如果存在可以通过汉明码校正操作来校正的错误，则执行该校正字，并且对校正字执行里德 - 所罗门码检测操作。如果汉明码不能校正错误，则对该字执行里德 - 所罗门码修正操作。

82. 发明申请

US20110122717A1 REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES 有权
标题翻译：在外部地址响应中更换记忆细胞的有缺陷的位点
公开(公告)号：US20110122717A1
公开(公告)日：2011-05-26
申请号：US13017168
申请日：2011-01-31
申请人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
发明人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
IPC分类号： G11C29/04
CPC分类号： G11C29/848
摘要： Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.
摘要翻译：提供控制器和存储器件。在一个实施例中，控制器被配置为响应于接收来自存储器单元的存储器单元的缺陷列的地址，来代替存储器件的存储器单元的无缺陷列来代替存储器件的存储器单元的缺陷列存储设备。在另一个实施例中，存储器设备具有存储单元的列，并且被配置为接收寻址存储器件的存储器单元列序列的无缺陷列的存储器单元的外部地址，而不是缺陷存储器列存储单元列的序列的单元，使得无缺陷列替代缺陷列。无缺陷列是可用于替换缺陷列的列序列中的缺陷列之后的邻近无缺陷列。

83. 发明申请

US20110122713A1 READ STROBE FEEDBACK IN A MEMORY SYSTEM 有权
标题翻译：在存储器系统中读取STROBE反馈
公开(公告)号：US20110122713A1
公开(公告)日：2011-05-26
申请号：US13021933
申请日：2011-02-07
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C7/22
CPC分类号： G11C7/1051 , G11C7/1063 , G11C16/26
摘要： A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus.
摘要翻译：控制器电路通过数据/ IO总线和控制总线耦合到存储器件。控制器电路产生读取使能信号，该信号被发送到存储器件以指示存储器件将数据驱动到数据/ IO总线上。读使能信号反馈到控制器电路，然后使用反馈信号从数据/ IO总线读取数据。

84. 发明授权

US07881134B2 Replacing defective columns of memory cells in response to external addresses 有权
标题翻译：根据外部地址更换存储单元的有缺陷的列
公开(公告)号：US07881134B2
公开(公告)日：2011-02-01
申请号：US12272138
申请日：2008-11-17
申请人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
发明人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells.
摘要翻译：提供了操作存储器件的电子系统和方法。在一个这样的实施例中，存储器装置接收外部地址，其代替存储器装置的存储器单元列的序列的不存在列的存储器单元的代替存储器列序列的存储器单元的缺陷列使得无缺陷存储器列替换缺陷存储器列。存储器单元的无缺陷列位于存储器单元列中的有缺陷列之后的存储器单元的缺陷列之后的非缺陷列，该存储器单元的列可用于替换存储单元的有缺陷的列。

85. 发明授权

US07810017B2 Variable sector-count ECC 有权
标题翻译：可变扇区数ECC
公开(公告)号：US07810017B2
公开(公告)日：2010-10-05
申请号：US11384965
申请日：2006-03-20
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C29/00
CPC分类号： H03M13/05 , G06F11/1068
摘要： Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a greater number of errors to be corrected by a combining the ECC codes in the coverage area without substantially changing the overall size of ECC codes being stored over a single sector approach. In one embodiment of the present invention, the size of the data block utilized for ECC coverage is variable and can be selected such that differing areas of the memory array or data types can have a differing ECC data coverage sizes. It is also noted that the ECC algorithm, math base or encoding scheme can also be varied between these differing areas of the memory array.
摘要翻译：描述了改进的存储器件，电路和数据方法，其通过增加由ECC代码覆盖的用户数据的数据区域来促进对存储器系统或器件中的数据的检测和校正。这样可以在更大的数据区域上平均任何可能的位错误，并且允许通过组合覆盖区域中的ECC码来校正更多数量的错误，而不会基本上改变通过单个扇区方法存储的ECC码的总体大小。在本发明的一个实施例中，用于ECC覆盖的数据块的大小是可变的，并且可以选择使得存储器阵列或数据类型的不同区域可以具有不同的ECC数据覆盖尺寸。还应注意的是，ECC算法，数学基础或编码方案也可以在存储器阵列的这些不同区域之间变化。

86. 发明申请

US20100251066A1 DATA HANDLING 有权
标题翻译：数据处理
公开(公告)号：US20100251066A1
公开(公告)日：2010-09-30
申请号：US12814885
申请日：2010-06-14
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/10 , B32B25/08 , B32B27/08 , F16L2011/047 , G06F11/1068 , G11C2029/0411
摘要： Methods and apparatus to facilitate determining or selecting a depth of error detection and/or error correction coverage, and detecting and/or correcting errors in data in accordance with the determined or selected depth of error detection and/or error correction coverage.
摘要翻译：便于确定或选择错误检测和/或纠错覆盖深度的方法和装置，以及根据所确定或选择的误差检测和/或纠错覆盖深度来检测和/或校正数据中的错误。

87. 发明申请

US20100124132A1 REPLACING DEFECTIVE COLUMNS OF MEMORY CELLS IN RESPONSE TO EXTERNAL ADDRESSES 有权
标题翻译：在外部地址响应中更换记忆细胞的有缺陷的位点
公开(公告)号：US20100124132A1
公开(公告)日：2010-05-20
申请号：US12272138
申请日：2008-11-17
申请人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
发明人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/848
摘要： Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective memory column replaces the defective memory column. The non-defective column of memory cells is proximate non-defective column of memory cells following the defective column of memory cells in the sequence of columns of memory cells that is available to replace the defective column of memory cells.
摘要翻译：提供了操作存储器件的电子系统和方法。在一个这样的实施例中，存储器装置接收外部地址，其代替存储器装置的存储器单元列的序列的不存在列的存储器单元的代替存储器列序列的存储器单元的缺陷列使得无缺陷存储器列替换缺陷存储器列。存储器单元的无缺陷列位于存储器单元列中的有缺陷列之后的存储器单元的缺陷列之后的非缺陷列，该存储器单元的列可用于替换存储单元的缺陷列。

88. 发明申请

US20080072120A1 Variable Strength ECC 有权
标题翻译：可变强度ECC
公开(公告)号：US20080072120A1
公开(公告)日：2008-03-20
申请号：US11513571
申请日：2006-08-31
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C29/00
CPC分类号： G06F11/10 , B32B25/08 , B32B27/08 , F16L2011/047 , G06F11/1068 , G11C2029/0411
摘要： Memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory controllers, memory systems, and/or non-volatile memory devices by allowing the number of ECC check bytes being utilized to be varied to increase or decrease the ECC check depth. This allows the depth of the ECC coverage (the overall number of bit errors detectable and/or correctable in each sector by the stored ECC check bytes) to be selected based on the application, the amount of available data storage for ECC check bytes in the overhead/spare area associated with the sector, the version of memory device or controller being utilized, or the number of errors being seen in the memory system, device, bank, erase block, or sector (the error incidence rate), while the base data size of the area (sector) covered by the ECC check bytes stays the same.
摘要翻译：描述的存储器件，电路和数据方法通过允许ECC校验字节的数量被改变来增加或减少，从而便于检测和校正存储器控制器，存储器系统和/或非易失性存储器件中的数据 ECC检查深度。这允许基于应用来选择ECC覆盖的深度（通过存储的ECC检查字节在每个扇区中可检测和/或可校正的位错误的总数），用于ECC中的ECC校验字节的可用数据存储量与扇区相关联的开销/备用区域，正在使用的存储设备或控制器的版本，或存储器系统，设备，存储体，擦除块或扇区中的错误数量（错误发生率），而基础由ECC检查字节覆盖的区域（扇区）的数据大小保持不变。

89. 发明授权

US08934306B2 Memory and sense parameter determination methods 有权
标题翻译：记忆和感测参数确定方法
公开(公告)号：US08934306B2
公开(公告)日：2015-01-13
申请号：US13413130
申请日：2012-03-06
申请人： Zhenlei Shen , William H. Radke
发明人： Zhenlei Shen , William H. Radke
IPC分类号： G11C7/06 , G11C11/34 , G11C7/10
CPC分类号： G11C16/26 , G11C7/06 , G11C7/08 , G11C7/1006 , G11C11/56 , G11C11/5642 , G11C13/004 , G11C29/026 , G11C2013/0054 , G11C2013/0057 , G11C2207/2254 , G11C2211/5634
摘要： Memory devices and methods for operating a memory include filtering a histogram of sensed data of the memory, and adjusting a parameter used to sense the memory using the filtered histogram. Filtering can be accomplished by averaging or summing, and may include weighting the sums or averages.
摘要翻译：用于操作存储器的存储器件和方法包括对存储器的感测数据的直方图进行滤波，以及使用滤波的直方图调整用于感测存储器的参数。可以通过平均或相加来实现滤波，并且可以包括加权和平均值。

90. 发明授权

US08902653B2 Memory devices and configuration methods for a memory device 有权
标题翻译：存储器件的存储器件和配置方法
公开(公告)号：US08902653B2
公开(公告)日：2014-12-02
申请号：US13208802
申请日：2011-08-12
申请人： William H. Radke , Tommaso Vali , Michele Incarnati
发明人： William H. Radke , Tommaso Vali , Michele Incarnati
IPC分类号： G11C11/34 , G11C16/06 , G06F11/10 , G11C16/10 , G11C16/04 , G11C11/56
CPC分类号： G06F11/1048 , G06F3/0604 , G06F3/0608 , G06F3/0629 , G06F3/0631 , G06F3/064 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G06F12/0207 , G06F12/0646 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/52
摘要： Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device.
摘要翻译：公开了存储器件和操作存储器件的方法。在一种这样的方法中，不同的存储器单元块具有用户数据空间和开销数据空间的不同配置。在至少一种方法中，开销数据分布在多于一个存储单元块内。在另一种方法中，可以响应于存储在存储器设备中的特定操作模式和/或用户数据的可靠性的期望级别重新配置块。

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