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81. 发明授权

US07202535B2 Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure 有权
标题翻译：集成半导体结构的制造方法和相应的集成半导体结构
公开(公告)号：US07202535B2
公开(公告)日：2007-04-10
申请号：US11183224
申请日：2005-07-14
申请人： Matthias Goldbach , Dongping Wu
发明人： Matthias Goldbach , Dongping Wu
IPC分类号： H01L29/94
CPC分类号： H01L21/823857
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1) is a n-MOSFET region and second transistor region (T2) is a p-MOSFET region; forming a gate structure on said first and second transistor region (T1, T2) including at least one gate dielectric layer (2, 3, 10c, 17, 25) and one gate layer (4; 35; 50, 60) in each of said first and second transistor regions (T1, T2); wherein said gate layer (4; 35; 60) in said second transistor region (T2) is made of negatively doped polysilicon; wherein said at least one gate dielectric layer (2, 10c, 17) in said first transistor region (T1) comprises a first dielectric layer (2, 10c, 17); wherein said at least one gate dielectric layer (2, 3, 10c, 25, 25′) in said second transistor region (T2) comprises an interfacial dielectric layer (2; 25; 25′) located adjacent to said gate layer (4; 35; 60) in said second transistor region (T2), which interfacial dielectric layer (2; 25; 25′) forms an Al2O3 containing interface on said gate layer (4; 35; 60) in said second transistor region (T2) causing a Fermi-pinning effect; and wherein said first transistor region (T1) does not include said interfacial dielectric layer (2; 25; 25′).
摘要翻译：本发明提供了一种用于集成半导体结构和相应的集成半导体结构的制造方法。该制造方法包括以下步骤：提供具有上表面（O）并具有第一和第二晶体管区域（T 1，T 2）的半导体衬底（1）; 其中所述第一晶体管区域（T 1）是n-MOSFET区域，第二晶体管区域（T 2）是p-MOSFET区域; 在包括至少一个栅极介电层（2,3,10c，17,25）和一个栅极层（4; 35; 50,60）的所述第一和第二晶体管区域（T 1，T 2）上形成栅极结构，在所述第一和第二晶体管区域（T 1，T 2）的每一个中; 其中所述第二晶体管区域（T 2）中的所述栅极层（4; 35; 60）由负掺杂多晶硅制成; 其中所述第一晶体管区域（T 1）中的所述至少一个栅介质层（2,10c，17）包括第一介电层（2,10c，17）; 其中所述第二晶体管区域（T 2）中的所述至少一个栅极电介质层（2,3，10c，25,25'）包括邻近所述栅极层的界面电介质层（2; 25; 25'） 4; 35; 60）在所述第二晶体管区域（T 2）中，所述界面电介质层（2; 25; 25'）形成含有Al 2 N 3 O 3界面在所述第二晶体管区域（T 2）中的所述栅极层（4; 35; 60）上引起费米钉扎效应; 并且其中所述第一晶体管区域（T 1）不包括所述界面电介质层（2; 25; 25'）。

82. 发明申请

US20070057304A1 Capacitor structure, memory cell and method for forming a capacitor structure 审中-公开
标题翻译：电容结构，存储单元及形成电容器结构的方法
公开(公告)号：US20070057304A1
公开(公告)日：2007-03-15
申请号：US11223145
申请日：2005-09-12
申请人： Tim Boescke , Matthias Goldbach
发明人： Tim Boescke , Matthias Goldbach
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/1087
摘要： The present invention refers to a trench capacitor structure as it is used in memory cells, for example in memory cells of memory devices. Particularly, the capacitor structure may be used in a DRAM memory. Furthermore, the invention relates to a memory cell comprising a transistor and a capacitor with a trench capacitor structure arranged in a semiconductor substrate. Furthermore, the invention relates to a DRAM comprising a memory cell with a transistor and a capacitor, whereby the capacitor comprises a trench capacitor structure. Moreover, the invention relates to a method for forming a capacitor structure in a semiconductor substrate.
摘要翻译：本发明涉及在存储单元中使用的沟槽电容器结构，例如在存储器件的存储单元中。特别地，电容器结构可以用在DRAM存储器中。此外，本发明涉及一种存储单元，其包括晶体管和具有布置在半导体衬底中的沟槽电容器结构的电容器。此外，本发明涉及包括具有晶体管和电容器的存储单元的DRAM，由此电容器包括沟槽电容器结构。此外，本发明涉及在半导体衬底中形成电容器结构的方法。

83. 发明授权

US07045855B2 Semiconductor device and corresponding fabrication method 失效
标题翻译：半导体器件及相应的制造方法
公开(公告)号：US07045855B2
公开(公告)日：2006-05-16
申请号：US10777207
申请日：2004-02-13
申请人： Björn Fischer , Matthias Goldbach , Stefan Jakschik , Till Schlösser
发明人： Björn Fischer , Matthias Goldbach , Stefan Jakschik , Till Schlösser
IPC分类号： H01L29/792
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31612 , H01L21/31616 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10838 , H01L27/1087 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L28/56 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/66181 , H01L29/785
摘要： A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.
摘要翻译：具有栅极结构的半导体器件，所述栅极结构具有由第一材料制成的第一栅极电介质，所述第一材料具有位于所述沟道区域正上方的第一厚度和第一介电常数，以及由第二栅极电介质构成的覆盖的第二栅极电介质材料具有明显大于第一介电常数的第二厚度和第二介电常数; 并且第一栅极电介质的第一厚度和第二栅极电介质的第二厚度被选择为使得具有第一栅极电介质的栅极结构的相应厚度以获得相同的阈值电压至少与厚度等于第一厚度和第二厚度之和的厚度。本发明还涉及相应的制造方法。

84. 发明申请

US20050285150A1 Field effect transistor, transistor arrangement and method for producing a semiconducting monocrystalline substrate and a transistor arrangement 有权
标题翻译：场效应晶体管，晶体管布置和用于制造半导体单晶衬底和晶体管布置的方法
公开(公告)号：US20050285150A1
公开(公告)日：2005-12-29
申请号：US11131938
申请日：2005-05-17
申请人： Albert Birner , Matthias Goldbach
发明人： Albert Birner , Matthias Goldbach
IPC分类号： H01L21/335 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/085 , H01L29/745
CPC分类号： H01L29/7846 , H01L21/76224 , H01L21/823807 , H01L21/823878
摘要： In order to insulate active areas of n-type FETs (91) and p-type FETs (92), insulator structures (21n, 21p, 22n, 22p) which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas (11n, 11p), and which stress them accordingly, are provided in the semiconductor substrate (1) in addition to the active areas (11n, 11p) formed by sections of a semiconductor substrate (1). The insulator structures (21n, 21p, 22n, 22p) are respectively established on a base section (211) by which a tensile stress is induced in adjacent active areas (21n). Insulator structures (21p, 22p) respectively next to a p-type FET (92) are selectively provided with additional buffer layers (61) by which, due to production, a compressive stress is induced in adjacent structures. The charge carrier mobility is increased both for electrons I n the channel regions (112n) of the n-type FETs (91) and for holes in the channel regions (112p) of the p-type FETs (92), and the functionality is improved both for the n-type FETs (91) and for the p-type FETs (92).
摘要翻译：为了使n型FET（91）和p型FET（92）的有源区域绝缘，由于生产而产生拉伸应力或压缩应力的绝缘体结构（21n，21p，22n，22p）在相应的相邻有效区域（11n，11p）上并且相应地施加它们，除了由半导体衬底的部分形成的有源区域（11n，11p）之外还设置在半导体衬底（1）中 1）。绝缘体结构（21n，21p，22n，22p）分别建立在相邻有效区域（21n）中引起拉伸应力的基部（211）上。分别在p型FET（92）旁边的绝缘体结构（21p，22p）选择性地设置有额外的缓冲层（61），由此产生在相邻结构中产生压缩应力。对于n型FET（91）的沟道区（112n）的电子和p型FET（92）的沟道区（112 p）中的空穴，电荷载流子迁移率都增加，对于n型FET（91）和p型FET（92），功能性都得到改善。

85. 发明申请

US20050275046A1 MULTI-LAYER GATE STACK STRUCTURE COMPRISING A METAL LAYER FOR A FET DEVICE, AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：包含用于FET器件的金属层的多层栅格堆叠结构及其制造方法
公开(公告)号：US20050275046A1
公开(公告)日：2005-12-15
申请号：US10865763
申请日：2004-06-14
申请人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
发明人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
IPC分类号： H01L21/28 , H01L21/3205 , H01L31/062
CPC分类号： H01L21/28044
摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.
摘要翻译：通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中，过渡金属是钛，钽或钴。对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。在将多晶硅层图案化之前打开氮化物衬垫。作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

86. 发明授权

US06903454B2 Contact spring configuration for contacting a semiconductor wafer and method for producing a contact spring configuration 失效
标题翻译：用于接触半导体晶片的接触弹簧构造和用于产生接触弹簧构造的方法
公开(公告)号：US06903454B2
公开(公告)日：2005-06-07
申请号：US10324874
申请日：2002-12-20
申请人： Matthias Goldbach , Albert Birner , Martin Franosch
发明人： Matthias Goldbach , Albert Birner , Martin Franosch
IPC分类号： G01R1/067 , G01R1/073 , H01L23/48
CPC分类号： G01R1/06727 , G01R1/07357 , G01R3/00 , H01L2924/0002 , H01L2924/00
摘要： A contact spring configuration for contacting semiconductor wafers is provided. At least one strip-type contact spring is provided on a substrate. The contact spring is fixed to a surface of the substrate on one side and is composed of a semiconductor material having a stress gradient which causes a permanent bending of the contact spring. The stress gradient in the semiconductor material is brought about by two semiconductor layers which are connected to one another and are mechanically strained differently. The different strains can be set by different doping or by deposition temperatures of different magnitude during the deposition of the semiconductor layers. The contact springs provide a good ohmic contact in particular with contact regions of a semiconductor wafer that are composed of a semiconductor material.
摘要翻译：提供了用于接触半导体晶片的接触弹簧构造。至少一个带状接触弹簧设置在基板上。接触弹簧在一侧固定到基板的表面，并且由具有引起接触弹簧的永久弯曲的应力梯度的半导体材料构成。半导体材料中的应力梯度由彼此连接并且机械应变不同的两个半导体层引起。可以通过不同的掺杂或通过在半导体层的沉积期间具有不同大小的沉积温度来设置不同的应变。接触弹簧特别提供了由半导体材料构成的半导体晶片的接触区域的良好欧姆接触。

87. 发明授权

US06873000B2 Storage cell field and method of producing the same 失效
标题翻译：储存池场及其生产方法
公开(公告)号：US06873000B2
公开(公告)日：2005-03-29
申请号：US10266188
申请日：2002-10-07
申请人： Matthias Goldbach , Till Schlösser
发明人： Matthias Goldbach , Till Schlösser
IPC分类号： H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/0218 , H01L27/10861 , H01L27/10867
摘要： A storage cell field has a plurality of storage cells formed in a substrate of a first doping type, said storage cells comprising a trench capacitor arranged in said substrate and a selection transistor associated with said trench capacitor and provided with a transistor body which is arranged in said substrate. An implantation having an increased dopant concentration of the first doping type is provided in said substrate. This implantation prevents space-charge zones, which are located at the trench capacitors and which are caused in predetermined storage states of said trench capacitors, from constricting a substrate region, which is available for applying a predetermined potential to the transistor bodies, in such a way that said predetermined potential cannot be applied.
摘要翻译：存储单元场具有形成在第一掺杂类型的衬底中的多个存储单元，所述存储单元包括布置在所述衬底中的沟槽电容器和与所述沟槽电容器相关联的选择晶体管，所述晶体管本体被布置在所述基板。在所述衬底中提供具有增加的第一掺杂类型的掺杂剂浓度的注入。这种注入防止位于沟槽电容器处并且在所述沟槽电容器的预定存储状态下引起的空间电荷区域将这种可用于向晶体管体施加预定电位的衬底区域收缩不能应用所述预定电位的方式。

88. 发明授权

US06864188B2 Semiconductor configuration and process for etching a layer of the semiconductor configuration using a silicon-containing etching mask 有权
标题翻译：半导体构造和使用含硅蚀刻掩模蚀刻半导体构造层的工艺
公开(公告)号：US06864188B2
公开(公告)日：2005-03-08
申请号：US10454518
申请日：2003-06-04
申请人： Matthias Goldbach
发明人： Matthias Goldbach
IPC分类号： H01L21/3065 , H01L21/033 , H01L21/302 , H01L21/308 , H01L21/311
CPC分类号： H01L21/0332 , H01L21/0335 , H01L21/31116 , H01L21/31144
摘要： To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or into an etching gas. The additional substance is present in the mask layer or a concentration of the additional substance can be subsequently increased in the mask layer. During a subsequent etching process for patterning using the mask layer, the mask layer is removed at a reduced etching rate.
摘要翻译：为了提高耐腐蚀性和降低含硅掩模层的蚀刻速率，将另外的物质混入掩模层或蚀刻气体中。另外的物质存在于掩模层中，或者可以在掩模层中随后增加附加物质的浓度。在随后的使用掩模层进行图案化的蚀刻工艺中，以降低的蚀刻速率除去掩模层。

89. 发明授权

US06861312B2 Method for fabricating a trench structure 失效
标题翻译：沟槽结构的制造方法
公开(公告)号：US06861312B2
公开(公告)日：2005-03-01
申请号：US10233969
申请日：2002-09-03
申请人： Albert Birner , Matthias Goldbach , Joern Luetzen
发明人： Albert Birner , Matthias Goldbach , Joern Luetzen
IPC分类号： H01L21/334 , H01L21/762 , H01L21/763 , H01L21/8242
CPC分类号： H01L21/76232 , H01L21/763 , H01L27/1087 , H01L29/66181
摘要： An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to be formed, in particular, a base region thereof. At least part of the widened region is then provided with a material region for the insulation region.
摘要翻译：通过首先加宽待形成的沟槽的第一沟槽区域，特别是其基极区域，形成用于DRAM的沟槽结构中的绝缘区域，例如氧化物环。然后至少部分加宽区域设置有用于绝缘区域的材料区域。

90. 发明授权

US06821861B1 Method for fabricating an electrode arrangement for charge storage 失效
标题翻译：用于制造用于电荷存储的电极装置的方法
公开(公告)号：US06821861B1
公开(公告)日：2004-11-23
申请号：US10631554
申请日：2003-07-31
申请人： Matthias Goldbach , Thomas Hecht
发明人： Matthias Goldbach , Thomas Hecht
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L27/10867
摘要： The invention relates to an electrode arrangement for charge storage with an external trench electrode (202; 406), embodied along the wall of a trench provided in a substrate (401) and electrically insulated on both sides in the trench by a first and a second dielectric (104; 405, 409); an internal trench electrode (201; 410), serving as counter-electrode to the external trench electrode (201; 406) and insulated by the second dielectric (104; 409) and a substrate electrode (201; 403), which is insulated by the first dielectric (104; 405) outside the trench, which serves as counter-electrode to the external trench electrode (202; 406) and is connected to the internal trench electrode (201; 410) in the upper trench region.
摘要翻译：本发明涉及一种用于电荷存储的电极装置，其具有外部沟槽电极（202; 406），其沿着设置在衬底（401）中的沟槽的壁体现，并且在沟槽的两侧通过第一和第二电介质（104; 405,409）; 用作与所述外部沟槽电极（201; 406）相反并被所述第二电介质（104,409）绝缘的对电极的内部沟槽电极（201; 410）和由所述第二电介质（104; 409）绝缘的衬底电极在沟槽外部的第一电介质（104; 405），其用作与外部沟槽电极（202; 406）的对电极，并且连接到上部沟槽区域中的内部沟槽电极（201; 410）。

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