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    • 88. 发明申请
    • SILVER-WHITE COPPER ALLOY AND METHOD OF PRODUCING SILVER-WHITE COPPER ALLOY
    • 银白铜合金和生产银白铜合金的方法
    • US20140112822A1
    • 2014-04-24
    • US14115062
    • 2012-06-27
    • Shinji TanakaKeiichiro OishiHiroharu Ogawa
    • Shinji TanakaKeiichiro OishiHiroharu Ogawa
    • C22C9/04
    • C22C9/04C22F1/08
    • Provided are a silver-white copper alloy which has superior mechanical properties such as hot workability, cold workability, or press property, color fastness, bactericidal and antibacterial properties, and Ni allergy resistance; and a method of producing such a silver-white copper alloy. The silver-white copper alloy includes 51.0 mass % to 58.0 mass % of Cu; 9.0 mass % to 12.5 mass % of Ni; 0.0003 mass % to 0.010 mass % of C; 0.0005 mass % to 0.030 mass % of Pb; and the balance of Zn and inevitable impurities, in which a relationship of 65.5≦[Cu]+1.2×[Ni]≦70.0 is satisfied between a content of Cu [Cu] (mass %) and a content of Ni [Ni] (mass %). In a metal structure thereof, an area ratio of β phases dispersed in an α-phase matrix is 0% to 0.9%.
    • 提供具有优异的机械性能如热加工性,冷加工性或冲压性,耐色牢度,杀菌和抗菌性能以及耐镍过敏性的银白铜合金。 以及制造这种银白铜合金的方法。 银白色铜合金含有Cu:51.0质量%〜58.0质量% 9.0质量%〜12.5质量%的Ni; 0.0003质量%〜0.010质量% 0.0005质量%至0.030质量%的Pb; 在Cu [Cu](质量%)的含量与Ni [Ni(Ni))含量之间,满足65.5≦̸ [Cu] + 1.2×[Ni] / nlE; 70.0的关系的Zn和不可避免的杂质的平衡 ](质量%)。 在其金属结构中,面积比为&bgr; 分散在α相基体中的相为0〜0.9%。
    • 90. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08547723B2
    • 2013-10-01
    • US13398418
    • 2012-02-16
    • Shinji TanakaMakoto YabuuchiYuta Yoshida
    • Shinji TanakaMakoto YabuuchiYuta Yoshida
    • G11C8/08
    • G11C11/419G11C5/06G11C5/063G11C7/08G11C7/227G11C8/08G11C8/10G11C11/415G11C11/418
    • A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    • 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如,半导体器件设置有与适当的位线相对布置的虚拟位线,以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管,其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线,并且对应于负载电容,建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时,采用虚拟位线信号。