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81. 发明申请

US20080239945A1 PERIPHERAL COMPONENT SWITCH HAVING AUTOMATIC LINK FAILOVER 有权
标题翻译：具有自动链路故障的外围组件开关
公开(公告)号：US20080239945A1
公开(公告)日：2008-10-02
申请号：US11694235
申请日：2007-03-30
申请人： Thomas A. Gregg
发明人： Thomas A. Gregg
IPC分类号： G06F11/00
CPC分类号： G06F11/2005 , G06F11/1443 , G06F11/2094
摘要： Disclosed are a PCI switch assembly, having automatic link failover, and a computer system including that switch assembly. The switch assembly comprises first and second interconnected, peripheral component switches. Each of the these switches has first and second primary ports and a plurality of secondary ports. The switch assembly has a normal mode and a failover mode. In the normal mode, each switch routes data through the switch to the secondary ports of the switch. In the failover mode, a failover path is defined and data are routed from the first switch to the second switch and then to one of the secondary ports of the second switch. The second switch detects a predefined fail condition, and changes the switch assembly from the normal mode to the failover mode in response to detecting the predefined fail condition.
摘要翻译：公开了具有自动链路故障切换的PCI开关组件以及包括该开关组件的计算机系统。开关组件包括第一和第二互连的外围部件开关。这些开关中的每一个具有第一和第二主端口和多个次端口。交换机组件具有正常模式和故障切换模式。在正常模式下，每个交换机将数据通过交换机路由到交换机的辅助端口。在故障切换模式下，定义了故障切换路径，数据从第一个交换机路由到第二个交换机，然后到第二个交换机的一个辅助端口。响应于检测到预定义的失败条件，第二交换机检测到预定义的失败状况，并将交换机组件从正常模式改变为故障切换模式。

82. 发明申请

US20080168186A1 I/O Adapter LPAR Isolation With Assigned Memory Space Using PCIe Requestor IDs 有权
标题翻译： I / O适配器LPAR隔离与分配的内存空间使用PCIe请求者ID
公开(公告)号：US20080168186A1
公开(公告)日：2008-07-10
申请号：US11621334
申请日：2007-01-09
申请人： Thomas A. Gregg
发明人： Thomas A. Gregg
IPC分类号： G06F3/00
CPC分类号： G06F13/124
摘要： A data processing system and method of isolating a plurality of I/O adapters in the system. The data processing system also comprises a set of processors communicating with the I/O adapters using a PCIe protocol. Each of the I/O adapters has a respective ID. In the preferred embodiment the commands issued by the I/O adapters include a PCIe defined Requestor ID field including one or more of the Requestor IDs of I/O Adapters. The Req IDs can be used as an input to a CAM which provides an index to a TVT to identify a unique and independent system memory space for the I/O adapter.
摘要翻译：一种隔离系统中的多个I / O适配器的数据处理系统和方法。数据处理系统还包括使用PCIe协议与I / O适配器通信的一组处理器。每个I / O适配器都有相应的ID。在优选实施例中，I / O适配器发出的命令包括PCIe定义的请求者ID字段，其包括I / O适配器的请求者ID中的一个或多个。 Req ID可用作CAM的输入，该CAM为TVT提供索引，以识别I / O适配器的唯一且独立的系统内存空间。

83. 发明申请

US20080148008A1 Moving, Resizing, and Memory Management for Producer-Consumer Queues 失效
标题翻译：生产者 - 消费者队列的移动，调整大小和内存管理
公开(公告)号：US20080148008A1
公开(公告)日：2008-06-19
申请号：US12028905
申请日：2008-02-11
申请人： Richard L. Arndt , David F. Craddock , Ronald E. Fuhs , Thomas A. Gregg , Thomas Schlipf
发明人： Richard L. Arndt , David F. Craddock , Ronald E. Fuhs , Thomas A. Gregg , Thomas Schlipf
IPC分类号： G06F12/00
CPC分类号： G06F5/10
摘要： Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.
摘要翻译：提供用于在不停止所有活动的情况下移动和/或调整内存中生产者 - 消费者队列大小的系统，方法和软件产品，以便在移动过程中不丢失数据或意外重复数据。有一个软件消费者和一个硬件生产商，如主机通道适配器。

84. 发明申请

US20080098197A1 Method and System For Address Translation With Memory Windows 审中-公开
标题翻译：用于存储器Windows的地址转换的方法和系统
公开(公告)号：US20080098197A1
公开(公告)日：2008-04-24
申请号：US11551405
申请日：2006-10-20
申请人： David F. Craddock , Charles S. Graham , Thomas A. Gregg
发明人： David F. Craddock , Charles S. Graham , Thomas A. Gregg
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F12/1009
摘要： Disclosed are a method and system for address translation with memory windows. The method comprises the steps of designating a memory region having a set of virtual addresses, each virtual address having an associated real address; and providing one or more translation tables for translating the virtual addresses to the real addresses; A memory region protection table entry (MRPTE) defines access rights for the memory region, and includes one or more pointers to the one or more translation tables. A memory window is bound to the memory region to provide access to a subset of the virtual addresses. A memory window protection table entry (MWPTE) defines access rights for the memory window, and includes one or more pointers to the one or more translation tables to translate the subset of virtual addresses to real addresses.
摘要翻译：公开了一种用于具有存储器窗口的地址转换的方法和系统。该方法包括以下步骤：指定具有一组虚拟地址的存储器区域，每个虚拟地址具有相关联的真实地址; 以及提供用于将虚拟地址转换为真实地址的一个或多个转换表; 存储器区域保护表条目（MRPTE）定义了存储器区域的访问权限，并且包括一个或多个指向一个或多个转换表的指针。存储器窗口被绑定到存储器区域以提供对虚拟地址的子集的访问。存储器窗口保护表条目（MWPTE）定义了存储器窗口的访问权限，并且包括一个或多个指向一个或多个转换表的指针，以将虚拟地址的子集转换为实际地址。

85. 发明申请

US20070299963A1 DETECTION OF INCONSISTENT DATA IN COMMUNICATIONS NETWORKS 有权
标题翻译：检测通信网络中的不确定性数据
公开(公告)号：US20070299963A1
公开(公告)日：2007-12-27
申请号：US11426421
申请日：2006-06-26
申请人： Casimer M. DeCusatis , Thomas A. Gregg
发明人： Casimer M. DeCusatis , Thomas A. Gregg
IPC分类号： G06F15/173
CPC分类号： H04L12/66
摘要： Inconsistent data in communications networks is detected. The detection is performed by a component of the network that is separate from where the recovery takes place. The detection employs a packet sequence number, which is checked when the packet is received. The packet sequence number is initialized to define a valid window of packet sequence numbers.
摘要翻译：检测到通信网络中不一致的数据。检测由网络的与恢复发生位置分开的组件执行。检测采用分组序列号，在接收到分组时检查该序列号。分组序列号被初始化以定义分组序列号的有效窗口。

86. 发明授权

US06995695B1 System, method, and article of manufacture for synchronizing running disparity values in a computer and a data demapping device 有权
标题翻译：用于在计算机和数据解映射设备中同步运行视差值的系统，方法和制造
公开(公告)号：US06995695B1
公开(公告)日：2006-02-07
申请号：US11046394
申请日：2005-01-28
申请人： Casimer Maurice DeCusatis , Thomas A. Gregg
发明人： Casimer Maurice DeCusatis , Thomas A. Gregg
IPC分类号： H03M7/00
CPC分类号： H04L25/4908 , H04J3/1617
摘要： A system and a method for synchronizing running disparity values in a first computer and a data demapping device are provided. The method includes generating a plurality of data characters and a synchronization control character. The method further includes iteratively determining a first running disparity value based on each character of the plurality of data characters and the synchronization control character. The method further includes encapsulating a first plurality of data characters and the synchronization control character from a computer into at least one GFP data block and transmitting the GFP data block to data demapping device. The method further includes decoding the GFP data block to obtain the plurality of data characters and the synchronization control character and iteratively determining a second running disparity value based on each character of the plurality of data characters and the synchronization control character. The method further includes setting the second running disparity value in the data demapping device equal to either a positive running disparity value or a negative running disparity value based on the synchronization control character to synchronize the second running disparity value and the first running disparity value.
摘要翻译：提供了一种用于在第一计算机和数据解映射设备中同步运行视差值的系统和方法。该方法包括生成多个数据字符和同步控制字符。该方法还包括基于多个数据字符和同步控制字符的每个字符反复地确定第一行进视差值。该方法还包括将来自计算机的第一多个数据字符和同步控制字符封装到至少一个GFP数据块中，并将GFP数据块发送到数据解映射设备。该方法还包括解码GFP数据块以获得多个数据字符和同步控制字符，并且基于多个数据字符和同步控制字符的每个字符迭代地确定第二行进视差值。该方法还包括基于同步控制字符将数据解映射设备中的第二运行视差值设置为等于正运行视差值或负运行视差值，以使第二运行视差值与第一运行视差值同步。

87. 发明授权

US06877047B2 Operating a coupling channel in a plurality of modes 失效
标题翻译：以多种模式操作耦合通道
公开(公告)号：US06877047B2
公开(公告)日：2005-04-05
申请号：US09960022
申请日：2001-09-21
申请人： Thomas A. Gregg , Kulwant M. Pandey
发明人： Thomas A. Gregg , Kulwant M. Pandey
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/12
摘要： A method and system for an I/O coupling channel to operate in a plurality of modes. The first mode is the new mode providing peer operation with many times more message passing facilities as the old mode. The second mode is used to connect the new channels through a converter to multiple old channels. In this mode, the new channel distributes its message passing resources among the multiple sink ports of the converter that are attached to old channels. The converter keeps no state information and only adjusts line speeds, routs outbound packets, and adds source information to inbound packets. The new channel operating in old compatibility mode gives the illusion to the software of multiple separate channels, one for each converter sink port.
摘要翻译：一种用于以多种模式操作的I / O耦合通道的方法和系统。第一种模式是提供对等操作的新模式，具有多种消息传递功能作为旧模式。第二种模式用于通过转换器将新通道连接到多个旧通道。在这种模式下，新信道在连接到旧信道的转换器的多个宿端口之间分配其消息传递资源。转换器不保留状态信息，只调整线路速率，路由出站数据包，并将源信息添加到入站数据包。以旧兼容性模式运行的新通道为多个独立通道的软件提供了错误，每个转换器接口端口都有一个通道。

88. 发明授权

US5610945A System for identifying communication sequences transmitted across multiple carriers by examining bit streams for sequences of valid words 失效
标题翻译：用于通过检查有效字序列的比特流来识别通过多个载波发送的通信序列的系统
公开(公告)号：US5610945A
公开(公告)日：1997-03-11
申请号：US477927
申请日：1995-06-07
申请人： Thomas A. Gregg , Joseph M. Hoke , Kulwant M. Pandey
发明人： Thomas A. Gregg , Joseph M. Hoke , Kulwant M. Pandey
IPC分类号： H04J3/06 , H04J14/00 , H04L25/14 , H04L29/06 , H04L29/04
CPC分类号： H04L29/06 , H04J3/0629 , H04L25/14 , H04J14/00 , H04L69/14
摘要： A system and method for asynchronously receiving data blocks, in parallel, across multiple fibers in a serial manner. Frame groups are provided as a mechanism to transmit associated data serially on each fiber and tie the data being transmitted together. The frame groups do not have sequence numbers, therefore, the receiver determines which frames are part of a frame group by the arrival times of the individual frames. The transceivers for each member of the parallel bus examine the received bit stream to extract frames and continuous sequences. For each member of the parallel bus there are independent receive buffers, and these buffers are controlled by independent states. The states inhibit erroneously generated frames from corrupting the contents of the receive buffers and inhibit the loading of the buffers after errors on the link. These states also control the loading of the receive buffers after retransmission of a buffer area. The information from the individual frames of the frame group is assembled in the proper sequence by another element in the channel. This element also suppresses notification of the intermediate frame groups when multiple frame groups are used to transmit a buffer area.
摘要翻译：一种用于以串行方式并行跨多条光纤异步接收数据块的系统和方法。帧组被提供为用于在每个光纤上串行发送相关数据并将正在发送的数据结合在一起的机制。帧组不具有序列号，因此，接收机根据各个帧的到达时间确定哪些帧是帧组的一部分。并行总线的每个成员的收发器检查接收到的比特流以提取帧和连续序列。对于并行总线的每个成员，都有独立的接收缓冲区，这些缓冲区由独立状态控制。这些状态禁止错误地产生的帧破坏接收缓冲器的内容，并且在链路上的错误之后禁止缓冲器的加载。这些状态还控制重发缓冲区之后的接收缓冲器的加载。来自帧组的各个帧的信息以正确的顺序由通道中的另一个元素组装。当使用多个帧组来发送缓冲区时，该元素还抑制中间帧组的通知。

89. 发明授权

US09213661B2 Enable/disable adapters of a computing environment 有权
标题翻译：启用/禁用计算环境的适配器
公开(公告)号：US09213661B2
公开(公告)日：2015-12-15
申请号：US12821187
申请日：2010-06-23
申请人： Anthony F. Coneski , David Craddock , Mark S. Farrell , Charles W. Gainey, Jr. , Beth A. Glendening , Thomas A. Gregg , Dan F. Greiner , Ugochukwu C. Njoku
发明人： Anthony F. Coneski , David Craddock , Mark S. Farrell , Charles W. Gainey, Jr. , Beth A. Glendening , Thomas A. Gregg , Dan F. Greiner , Ugochukwu C. Njoku
IPC分类号： G06F3/00 , G06F13/28 , G06F13/38
CPC分类号： G06F13/385 , G06F13/28
摘要： An adapter is enabled for use. The enabling includes assigning one or more address spaces to the adapter, based on a request. For each address space assigned to the adapter, a corresponding device table entry is assigned. When the adapter is no longer needed, it is disabled and the assigned device table entries become available.
摘要翻译：适配器已启用使用。启用包括基于请求向适配器分配一个或多个地址空间。对于分配给适配器的每个地址空间，分配相应的设备表条目。当不再需要适配器时，它将被禁用，并且分配的设备表条目可用。

90. 发明授权

US08918573B2 Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment 有权
标题翻译：在外围组件互连快速（PCIe）环境中的输入/输出（I / O）扩展响应处理
公开(公告)号：US08918573B2
公开(公告)日：2014-12-23
申请号：US12821239
申请日：2010-06-23
申请人： Thomas A. Gregg , David F. Craddock , Eric N. Lais
发明人： Thomas A. Gregg , David F. Craddock , Eric N. Lais
IPC分类号： G06F13/20 , G06F13/40
CPC分类号： G06F13/4027 , G06F13/36 , G06F13/385
摘要： Embodiments of the invention relate to optimizing EDRAM refresh rates in a high performance cache architecture. A request is received from a requester to perform an operation on an I/O adapters. It is determined if the request is in a format other than a format supported by an I/O bus and if, the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus and is transmitted to the requester.
摘要翻译：本发明的实施例涉及在高性能高速缓存架构中优化EDRAM刷新率。从请求者接收到对I / O适配器执行操作的请求。确定请求是否是不同于I / O总线支持的格式的格式，如果请求者需要请求的完成响应。该请求被转换为I / O总线支持的格式，并被传送到I / O适配器。从I / O适配器接收到完成响应，并包括一个指示符，表示请求已经完成。完成响应采用I / O总线支持的格式，并传送到请求者。

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