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81. 发明申请

US20060231892A1 Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors 失效
标题翻译：增强的绝缘体上硅（SOI）晶体管和制造增强型SOI晶体管的方法
公开(公告)号：US20060231892A1
公开(公告)日：2006-10-19
申请号：US11106002
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L27/12
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

82. 发明申请

US20060172499A1 STRUCTURE AND METHOD FOR THIN BOX SOI DEVICE 有权
标题翻译：薄盒SOI器件的结构与方法
公开(公告)号：US20060172499A1
公开(公告)日：2006-08-03
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, comprising providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

83. 发明申请

US20060136858A1 Utilizing fuses to store control parameters for external system components 审中-公开
标题翻译：利用保险丝存储外部系统组件的控制参数
公开(公告)号：US20060136858A1
公开(公告)日：2006-06-22
申请号：US11016214
申请日：2004-12-17
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G11C17/18
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

84. 发明申请

US20060131743A1 Changing chip function based on fuse states 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20060131743A1
公开(公告)日：2006-06-22
申请号：US11016220
申请日：2004-12-17
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： H01L23/48
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

85. 发明申请

US20050212087A1 STRUCTURE AND METHOD OF MAKING A BIPOLAR TRANSISTOR HAVING REDUCED COLLECTOR-BASED CAPACITANCE 失效
标题翻译：具有减少集电极电容的双极晶体管的结构和方法
公开(公告)号：US20050212087A1
公开(公告)日：2005-09-29
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/102 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

86. 发明授权

US06940149B1 Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base 失效
标题翻译：形成在发射极和非本征基底之间具有空隙的双极晶体管的结构和方法
公开(公告)号：US06940149B1
公开(公告)日：2005-09-06
申请号：US10708563
申请日：2004-03-11
申请人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
发明人： Rama Divakaruni , Gregory Freeman , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/06 , H01L27/082 , H01L29/06 , H01L29/737 , H01L31/072
CPC分类号： H01L29/66242 , H01L27/0623 , H01L29/0649 , H01L29/7378
摘要： Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.
摘要翻译：提供了用于制造双极晶体管的结构和方法，双极晶体管包括集电极，覆盖集电极的本征基极，覆盖本征基极的发射极以及与发射极间隔开的非本征基极，该间隙至少包括一个气隙和一个真空空隙。

87. 发明申请

US20050167786A1 STRUCTURE AND METHOD FOR LOCAL RESISTOR ELEMENT IN INTEGRATED CIRCUIT TECHNOLOGY 有权
标题翻译：集成电路技术中的局部电阻元件的结构与方法
公开(公告)号：US20050167786A1
公开(公告)日：2005-08-04
申请号：US10708023
申请日：2004-02-03
申请人： Jason Gill , Terence Hook , Randy Mann , William Murphy , William Tonti , Steven Voldman
发明人： Jason Gill , Terence Hook , Randy Mann , William Murphy , William Tonti , Steven Voldman
IPC分类号： H01L21/8244 , H01L27/02 , H01L27/08 , H01L27/11 , H01L27/12 , H01L27/082
CPC分类号： H01L27/11 , H01L27/0288 , H01L27/0802 , H01L27/1112 , H01L27/1203 , H01L29/7304 , H01L29/7378 , H01L29/7391 , H01L29/78 , Y10S257/903 , Y10S257/904
摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.
摘要翻译：一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。

88. 发明申请

US20050087814A1 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US20050087814A1
公开(公告)日：2005-04-28
申请号：US10995444
申请日：2004-11-23
申请人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
发明人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94 , H01L21/8238
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

89. 发明授权

US06882027B2 Methods and apparatus for providing an antifuse function 有权
标题翻译：提供反熔丝功能的方法和装置
公开(公告)号：US06882027B2
公开(公告)日：2005-04-19
申请号：US10447018
申请日：2003-05-28
申请人： Axel Brintzinger , Carl Radens , William Tonti
发明人： Axel Brintzinger , Carl Radens , William Tonti
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.
摘要翻译：公开了用于提供反熔丝的方法和装置，其中反熔丝包括具有由浅沟槽隔离（STI）边界限定的有源区的半导体衬底; 栅极导体，其设置在所述半导体衬底上方并且覆盖所述STI边界的至少一部分; 设置在所述半导体衬底和所述栅极导体之间的电介质; 耦合到所述栅极导体的第一端子; 以及耦合到所述半导体衬底的第二端子，其中所述电介质的击穿导致所述栅极导体的区域和所述有源区域的区域之间的电连接包括基本上靠近所述STI边界。

90. 发明申请

US20050073354A1 VOLTAGE DIVIDER FOR INTEGRATED CIRCUITS 失效
标题翻译：用于集成电路的电压分压器
公开(公告)号：US20050073354A1
公开(公告)日：2005-04-07
申请号：US10605466
申请日：2003-10-01
申请人： Wagdi Abadeer , John Fifield , William Tonti
发明人： Wagdi Abadeer , John Fifield , William Tonti
IPC分类号： G11C5/14 , H01L27/08 , H01L27/088 , H02J1/00 , H02M3/00
CPC分类号： G11C5/147 , H01L27/0802 , H01L27/088 , H02M3/00
摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).
摘要翻译：用于集成电路的分压器，不包括使用电阻器。在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET1和NFET2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A1（未示出）的栅电极（16）和p衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A2（未示出）的栅电极（24）和p衬底（26）。 NFET1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET1和NFET2之间的电压差与VDD具有线性关系。结果，通过适当地选择各个晶体管栅电极区域（A1）和（A2）之间的比率，可以在NFET1和NFET2之间划分电压VDD。

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