专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明授权

US08803129B2 Patterning contacts in carbon nanotube devices 有权
标题翻译：碳纳米管器件中的图案接触
公开(公告)号：US08803129B2
公开(公告)日：2014-08-12
申请号：US13270648
申请日：2011-10-11
申请人： Josephine B Chang , Martin Glodde , Michael A. Guillorn
发明人： Josephine B Chang , Martin Glodde , Michael A. Guillorn
IPC分类号： H01L29/06 , H01L31/00 , H01L29/76 , H01L21/02 , H01L21/84 , H01L21/336 , H01L51/00 , H01L29/775 , H01L29/423
CPC分类号： H01L51/0048 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/775 , H01L51/055 , H01L51/102 , Y10S977/742 , Y10S977/938
摘要： A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.
摘要翻译：结构包括具有设置在表面上的碳纳米管（CNT）的基板。 CNT部分地设置在保护性电绝缘层内。该结构还包括设置在衬底上的栅极堆叠。未被保护电绝缘层覆盖的CNT的长度的第一部分通过栅极堆叠。源极和漏极触点设置成与栅极堆叠相邻，其中未被保护电绝缘层覆盖的CNT的长度的第二和第三部分导电地电耦合到源极和漏极触点。栅极堆叠以及源极和漏极触点包含在保护电绝缘层内并且设置在保护性电绝缘层之上的电绝缘的有机平坦化层内。还描述了制造CNT基晶体管的方法。

82. 发明授权

US08754530B2 Self-aligned borderless contacts for high density electronic and memory device integration 有权
标题翻译：用于高密度电子和存储器件集成的自对准无边界触点
公开(公告)号：US08754530B2
公开(公告)日：2014-06-17
申请号：US12193339
申请日：2008-08-18
申请人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
发明人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
IPC分类号： H01L23/48
CPC分类号： H01L21/76897 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.
摘要翻译：公开了一种制造具有自对准无边界电触头的晶体管的方法。栅极堆叠形成在硅区域上。在栅堆叠周围形成偏置的间隔物。包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。在牺牲层中限定图案以限定电接触的接触面积。该图案暴露了栅极堆叠和源极/漏极的至少一部分。沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。已经定义的高度的接触面积被金属化以形成电接触。

83. 发明授权

US08586449B1 Raised isolation structure self-aligned to fin structures 有权
标题翻译：升高的隔离结构自对准鳍结构
公开(公告)号：US08586449B1
公开(公告)日：2013-11-19
申请号：US13603872
申请日：2012-09-05
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
IPC分类号： H01L21/76
CPC分类号： H01L21/845 , H01L21/76229
摘要： Raised isolation structures can be formed at the same level as semiconductor fins over an insulator layer. A template material layer can be conformally deposited to fill the gaps among the semiconductor fins within each cluster of semiconductor fins on an insulator layer, while the space between adjacent clusters is not filled. After an anisotropic etch, discrete template material portions can be formed within each cluster region, while the buried insulator is physically exposed between cluster regions. A raised isolation dielectric layer is deposited and planarized to form raised isolation structures employing the template material portions as stopping structures. After removal of the template material portions, a cluster of semiconductor fins are located within a trench that is self-aligned to outer edges of the cluster of semiconductor fins. The trench can be employed to confine raised source/drain regions to be formed on the cluster of semiconductor fins.
摘要翻译：升高的隔离结构可以在与绝缘体层上的半导体鳍片相同的水平上形成。可以共形沉积模板材料层以填充绝缘体层上的每个半导体翅片簇内的半导体鳍片之间的间隙，而相邻簇之间的空间未被填充。在各向异性蚀刻之后，可以在每个簇区域内形成离散的模板材料部分，而埋入的绝缘体在簇区域之间物理暴露。沉积并平坦化凸起的隔离介电层以形成采用模板材料部分作为停止结构的凸起隔离结构。在去除模板材料部分之后，一组半导体鳍片位于与半导体鳍片簇的外边缘自对准的沟槽内。沟槽可以用来限制要形成在半导体鳍片簇上的凸起的源极/漏极区域。

84. 发明申请

US20130277758A1 Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric 有权
公开(公告)号：US20130277758A1
公开(公告)日：2013-10-24
申请号：US13451054
申请日：2012-04-19
申请人： Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
发明人： Josephine B. Chang , Michael A. Guillorn , Jeffrey W. Sleight
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823431 , H01L21/02134 , H01L21/0274 , H01L21/28017 , H01L21/823437 , H01L21/823828 , H01L21/845 , H01L27/0207 , H01L29/16 , H01L29/66545
摘要： A method of fabricating a FET device is provided that includes the following steps. A wafer is provided. At least one active area is formed in the wafer. A plurality of dummy gates is formed over the active area. Spaces between the dummy gates are filled with a dielectric gap fill material such that one or more keyholes are formed in the dielectric gap fill material between the dummy gates. The dummy gates are removed to reveal a plurality of gate canyons in the dielectric gap fill material. A mask is formed that divides at least one of the gate canyons, blocks off one or more of the keyholes and leaves one or more of the keyholes un-blocked. At least one gate stack material is deposited onto the wafer filling the gate canyons and the un-blocked keyholes. A FET device is also provided.

85. 发明授权

US08557648B2 Recessed source and drain regions for FinFETs 有权
公开(公告)号：US08557648B2
公开(公告)日：2013-10-15
申请号：US13348188
申请日：2012-01-11
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.

86. 发明授权

US08536018B1 Maskless inter-well deep trench isolation structure and methods of manufacture 有权
标题翻译：无掩膜深沟槽隔离结构及制造方法
公开(公告)号：US08536018B1
公开(公告)日：2013-09-17
申请号：US13467314
申请日：2012-05-09
申请人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
发明人： Brent A. Anderson , Andres Bryant , Josephine B. Chang , Michael A. Guillorn , Ryoji Hasumi , Edward J. Nowak , Mickey H. Yu
IPC分类号： H01L27/108
CPC分类号： H01L21/76283 , H01L21/76232 , H01L21/84
摘要： A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.
摘要翻译：提供了一种低功率无掩膜深沟槽隔离结构及其制造方法。一种方法包括在衬底上沉积多个层，并在多个层上形成层。该方法还包括在衬底中形成阱结构，以及在层的相对侧形成侧壁间隔物。该方法还包括通过去除侧壁间隔件和与通过去除侧壁间隔件形成的开口对准的衬底的部分，将衬底中的自对准深沟槽形成在阱结构下方。该方法还包括形成与深沟槽对准的浅沟槽。该方法还包括通过用绝缘体材料填充浅沟槽和深沟槽来形成浅沟槽隔离结构和深沟槽隔离结构。

87. 发明授权

US08466451B2 Single gate inverter nanowire mesh 失效
标题翻译：单门逆变器纳米线网
公开(公告)号：US08466451B2
公开(公告)日：2013-06-18
申请号：US13316515
申请日：2011-12-11
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L29/06 , H01L31/00 , H01L27/105 , H01L27/148
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

88. 发明授权

US08422273B2 Nanowire mesh FET with multiple threshold voltages 有权
标题翻译：具有多个阈值电压的纳米线网状FET
公开(公告)号：US08422273B2
公开(公告)日：2013-04-16
申请号：US12470159
申请日：2009-05-21
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： G11C11/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
摘要翻译：提供了基于纳米线的场效应晶体管（FET）及其制造技术。在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源区和漏区的多个纳米线通道，其中一个或多个的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。

89. 发明申请

US20130087860A1 BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS 有权
标题翻译：无边界自对准的金属接触方式使用可印制的电介质材料
公开(公告)号：US20130087860A1
公开(公告)日：2013-04-11
申请号：US13270047
申请日：2011-10-10
申请人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
发明人： Josephine B. Chang , Sebastian U. Engelmann , Nicholas C.M. Fuller , Michael A. Guillorn , Eric A. Joseph , Adam M. Pyzyna
IPC分类号： H01L27/092 , H01L21/283
CPC分类号： H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Borderless self-aligned metal contacts to high density complementary metal oxide semiconductor (CMOS) circuits and methods for constructing the same. An example method includes creating an enclosed region for metal deposition defined by the gates of the adjacent transistors and an opposing pair of dielectric walls adjacent to source regions and drain regions of the adjacent transistors. The method further includes depositing a metal layer within the enclosed region. The metal contacts thus formed are self-aligned to the enclosed regions.
摘要翻译：无边界自对准金属接触高密度互补金属氧化物半导体（CMOS）电路及其构造方法。示例性方法包括为相邻晶体管的栅极形成的用于金属沉积的封闭区域和邻近相邻晶体管的源极区域和漏极区域的相对的一对电介质壁。该方法还包括在封闭区域内沉积金属层。这样形成的金属触点与封闭区域自对准。

90. 发明申请

US20130026133A1 Method to Transfer Lithographic Patterns Into Inorganic Substrates 有权
标题翻译：将光刻图案转移到无机基板中的方法
公开(公告)号：US20130026133A1
公开(公告)日：2013-01-31
申请号：US13191985
申请日：2011-07-27
申请人： Sebastian Ulrich Engelmann , Martin Glodde , Michael A. Guillorn
发明人： Sebastian Ulrich Engelmann , Martin Glodde , Michael A. Guillorn
IPC分类号： C23F1/02
CPC分类号： H01L21/0337 , G03F7/0043 , G03F7/0757 , G03F7/094 , H01L21/0332
摘要： Techniques for minimizing or eliminating pattern deformation during lithographic pattern transfer to inorganic substrates are provided. In one aspect, a method for pattern transfer into an inorganic substrate is provided. The method includes the following steps. The inorganic substrate is provided. An organic planarizing layer is spin-coated on the inorganic substrate. The organic planarizing layer is baked. A hardmask is deposited onto the organic planarizing layer. A photoresist layer is spin-coated onto the hardmask. The photoresist layer is patterned. The hardmask is etched through the patterned photoresist layer using reactive ion etching (RIE). The organic planarizing layer is etched through the etched hardmask using RIE. A high-temperature anneal is performed in the absence of oxygen. The inorganic substrate is etched through the etched organic planarizing layer using reactive ion etching.
摘要翻译：提供了在将光刻图案转移到无机基底期间最小化或消除图案变形的技术。一方面，提供了图案转印到无机基板中的方法。该方法包括以下步骤。提供无机基材。将有机平面化层旋涂在无机基材上。烘烤有机平坦化层。硬掩模沉积在有机平坦化层上。将光致抗蚀剂层旋涂在硬掩模上。对光刻胶层进行图案化。使用反应离子蚀刻（RIE），通过图案化的光刻胶层蚀刻硬掩模。使用RIE蚀刻通过蚀刻的硬掩模的有机平坦化层。在不存在氧的情况下进行高温退火。使用反应离子蚀刻通过蚀刻的有机平坦化层蚀刻无机衬底。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式