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81. 发明授权

US07567457B2 Nonvolatile memory array architecture 有权
标题翻译：非易失性存储器阵列架构
公开(公告)号：US07567457B2
公开(公告)日：2009-07-28
申请号：US11929724
申请日：2007-10-30
申请人： Hagop Nazarian , Harry Kuo , Michael Achter
发明人： Hagop Nazarian , Harry Kuo , Michael Achter
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06
CPC分类号： G11C8/14 , G11C8/08 , G11C16/0416 , G11C16/0491 , G11C16/10
摘要： An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.
摘要翻译：一种包括多对非易失性存储器（“NVM”）单元的二维或三维阵列的装置，其被耦合以使能NVM单元的编程和擦除。多对NVM单元电连接到字线和位线。每对NVM单元包括第一存储单元和第二存储单元。第一和第二存储单元包括第一源极/漏极，第二源极/漏极和控制栅极。第一存储单元的第一源极/漏极连接到位线之一。第一存储单元的第二源极/漏极连接到第二存储单元的第一源极/漏极。第二存储单元的第二源极/漏极连接到另一个位线。第一和第二存储单元的控制栅极连接到不同的字线。

82. 发明申请

US20090113115A1 NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY 有权
标题翻译：非易失性存储器阵列分区结构和使用同一存储器中的单级电池和多级电池的方法
公开(公告)号：US20090113115A1
公开(公告)日：2009-04-30
申请号：US11928865
申请日：2007-10-30
申请人： Hagop Nazarian , Ali Pourkeramati
发明人： Hagop Nazarian , Ali Pourkeramati
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G11C11/5621 , G11C16/08 , G11C2211/5641
摘要： A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.
摘要翻译：公开了一种存储器件，并且包括存储器单元阵列和配置成以单级单元模式寻址阵列的第一部分的分区系统，以及以多级单元模式的阵列的第二部分。

83. 发明申请

US20070279033A1 Zero power start-up circuit for self-bias circuit 有权
标题翻译：用于自偏置电路的零功率启动电路
公开(公告)号：US20070279033A1
公开(公告)日：2007-12-06
申请号：US11891078
申请日：2007-08-09
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： G05F3/16
CPC分类号： G05F3/205 , Y10S323/901
摘要： An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its operation in its desired stable state. Once the self-bias circuit converges to its desired state of operation a start-up voltage reference/voltage clamping circuit shuts off current flow to the self-bias circuit and the start-up circuit enters a low power mode of operation to reduce its overall current and power draw. This allows for embodiments of the present invention to be utilized in portable and/or low power devices where low power consumption is of increased importance. In one embodiment of the present invention, a band-gap voltage reference circuit is initiated utilizing a start-up circuit.
摘要翻译：描述了用于自偏置电路的改进的启动电路和方法，其将启动电压和电流施加到自偏置电路以将其操作初始化为其所需的稳定状态。一旦自偏置电路收敛到其期望的操作状态，启动电压基准/电压钳位电路就切断到自偏压电路的电流，并且启动电路进入低功率运行模式以减小其整体电流和功率消耗。这允许将本发明的实施例用于低功耗增加重要性的便携式和/或低功率设备中。在本发明的一个实施例中，利用启动电路启动带隙电压参考电路。

84. 发明申请

US20070047326A1 Programming memory devices 有权
公开(公告)号：US20070047326A1
公开(公告)日：2007-03-01
申请号：US11546171
申请日：2006-10-11
申请人： Dzung Nguyen , Benjamin Louie , Hagop Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung Nguyen , Benjamin Louie , Hagop Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

85. 发明申请

US20060256620A1 Programming memory devices 有权
公开(公告)号：US20060256620A1
公开(公告)日：2006-11-16
申请号：US11126790
申请日：2005-05-11
申请人： Dzung Nguyen , Benjamin Louie , Hagop Nazarian , Aaron Yip , Jin-Man Han
发明人： Dzung Nguyen , Benjamin Louie , Hagop Nazarian , Aaron Yip , Jin-Man Han
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10
摘要： A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

86. 发明申请

US20060256618A1 Flash memory array using adjacent bit line as source 有权
公开(公告)号：US20060256618A1
公开(公告)日：2006-11-16
申请号：US11127466
申请日：2005-05-12
申请人： Hagop Nazarian
发明人： Hagop Nazarian
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/0491
摘要： A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines of the plurality of bit lines are adapted to operate as either source lines or bit lines in response to bit line selection and biasing.

87. 发明申请

US20050219902A1 Voltage booster 失效
公开(公告)号：US20050219902A1
公开(公告)日：2005-10-06
申请号：US11137941
申请日：2005-05-26
申请人： Hagop Nazarian , Dzung Nguyen
发明人： Hagop Nazarian , Dzung Nguyen
IPC分类号： G05F1/10 , G11C5/14 , G11C11/34 , G11C16/08 , G11C16/30 , H02M3/07
CPC分类号： G11C5/145 , G11C16/08 , G11C16/30 , H02M3/073
摘要： Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.

88. 发明申请

US20050093613A1 Voltage booster 有权
公开(公告)号：US20050093613A1
公开(公告)日：2005-05-05
申请号：US10701141
申请日：2003-11-04
申请人： Hagop Nazarian , Dzung Nguyen
发明人： Hagop Nazarian , Dzung Nguyen
IPC分类号： G05F1/10 , G11C5/14 , G11C11/34 , G11C16/08 , G11C16/30 , H02M3/07
CPC分类号： G11C5/145 , G11C16/08 , G11C16/30 , H02M3/073
摘要： Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND flash memory devices. The boosted voltage can be used as a gate voltage for a pass gate providing programming voltages to a selected block of memory cells, such as in a NAND flash memory array. The pass circuits facilitate the elimination of high-voltage p-channel devices by providing a boosted voltage using n-channel devices. The pass circuits further permit control of multiple pass gates using a single boosted voltage source.

89. 发明授权

US5502403A High speed configuration independent programmable macrocell 失效
标题翻译：高速配置独立的可编程宏单元
公开(公告)号：US5502403A
公开(公告)日：1996-03-26
申请号：US360469
申请日：1994-12-20
申请人： Lin-Shih Liu , Syed B. Raza , Hagop Nazarian , George M. Ansel , Stephen M. Douglass , Jeffery S. Hunt
发明人： Lin-Shih Liu , Syed B. Raza , Hagop Nazarian , George M. Ansel , Stephen M. Douglass , Jeffery S. Hunt
IPC分类号： H03K19/173 , H03K19/0948
CPC分类号： H03K19/1736
摘要： A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.
摘要翻译：用户可配置电路包含时钟逻辑，开关元件和数据路径电路。在开关元件中接收输入数据，并且开关元件和数据路径电路构成电路的整个数据路径。接收多个用户可配置输入以为特定用户应用配置电路。时钟逻辑和开关元件实现可由用户可配置输入配置的逻辑功能。逻辑功能在时钟逻辑中被预处理，从而在数据通路中发生最小的延迟。此外，通过开关元件和寄存器的传播延迟与用户可配置输入无关。本发明的用户可配置电路具有用作可编程逻辑器件的宏小区的应用，允许用户将电路配置为D型触发器，T型触发器。此外，用户选择输出电路的极性。

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