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81. 发明授权

US07688931B2 Space and power efficient hybrid counters array 失效
标题翻译：空间和功率高效的混合计数器阵列
公开(公告)号：US07688931B2
公开(公告)日：2010-03-30
申请号：US12120416
申请日：2008-05-14
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G06M3/00
CPC分类号： H03K21/026
摘要： A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
摘要翻译：用于计数事件的混合计数器阵列装置。混合计数器阵列包括包括N个计数器装置的第一计数器部分，每个计数器装置用于接收表示来自事件源的事件发生的信号，并提供对应于混合计数器阵列的较低位的第一计数值。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示混合计数器阵列的较高阶位的第二计数值。控制装置监视第一计数器部分的N个计数器装置中的每一个，并且启动更新存储在第二计数器部分中相应的可寻址存储器位置处的对应的第二计数值的值。因此，第一和第二计数值的组合提供了接收事件数量的瞬时量度。

82. 发明授权

US07532700B2 Space and power efficient hybrid counters array 失效
标题翻译：空间和功率高效的混合计数器阵列
公开(公告)号：US07532700B2
公开(公告)日：2009-05-12
申请号：US11507310
申请日：2006-08-21
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G06M3/00
CPC分类号： H03K21/026
摘要： A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
摘要翻译：用于计数事件的混合计数器阵列装置。混合计数器阵列包括包括N个计数器装置的第一计数器部分，每个计数器装置用于接收表示来自事件源的事件发生的信号，并提供对应于混合计数器阵列的较低位的第一计数值。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示混合计数器阵列的较高阶位的第二计数值。控制装置监视第一计数器部分的N个计数器装置中的每一个，并且启动更新存储在第二计数器部分中相应的可寻址存储器位置处的对应的第二计数值的值。因此，第一和第二计数值的组合提供了接收事件数量的瞬时量度。

83. 发明申请

US20090116610A1 LOW LATENCY COUNTER EVENT INDICATION 有权
标题翻译：低期计数器事件指示
公开(公告)号：US20090116610A1
公开(公告)日：2009-05-07
申请号：US12130724
申请日：2008-05-30
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G01F15/06 , G06M3/00
CPC分类号： H03K23/54
摘要： A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding “interrupt arm” bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.
摘要翻译：一种用于对具有中断指示进行计数事件的混合计数器阵列装置，包括包括N个计数器装置的第一计数器部分，每个计数器装置用于计数表示事件发生的信号，并提供表示较低位的第一计数值。与每个相应计数器装置相关联的溢出位装置响应于溢出状况被另外设置。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高阶位的第二计数值。操作耦合的控制设备监视每个相关联的溢出位设备并且响应于设置的相应溢出位而启动存储在相应存储器位置的第二计数值的递增。将增加的第二计数值与存储在阈值寄存器中的中断阈值进行比较，并且当第二计数器值等于中断阈值时，相应的“中断臂”位被设置为使能快速中断指示。在该计数器的低位后续翻转时，中断将被触发。

84. 发明授权

US07461383B2 Method and apparatus for efficient performance monitoring of a large number of simultaneous events 失效
标题翻译：用于高效率监测大量同时事件的方法和装置
公开(公告)号：US07461383B2
公开(公告)日：2008-12-02
申请号：US11507307
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F11/348 , Y02D10/34
摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.
摘要翻译：一种用于监视大量同时事件的系统实现了具有包括计数器装置的第一计数器部分的混合计数器阵列装置，每个计数器装置用于接收表示从事件源发生的事件的信号，并提供对应于较低次序的第一计数值混合计数器阵列的位。第二计数器部分包括具有与计数器装置对应的可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高阶位的第二计数值。控制装置监视每个计数器装置并且启动更新存储在相应的可寻址存储器位置处的对应的第二计数值的值。当与事件相关的计数值等于阈值时，该系统包括用于向处理器设备提供快速中断触发的中断预指示。数据传输子系统另外启用以下一个或多个：通过窄总线对第一和第二计数器部分中的计数值进行读访问或写入访问，用于初始化和确定计数状态的读/写访问响应于处理器设备请求的被监视事件类型的值。

85. 发明申请

US20080043899A1 Space and power efficient hybrid counters array 失效
标题翻译：空间和功率高效的混合计数器阵列
公开(公告)号：US20080043899A1
公开(公告)日：2008-02-21
申请号：US11507310
申请日：2006-08-21
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： H03K23/00
CPC分类号： H03K21/026
摘要： A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
摘要翻译：用于计数事件的混合计数器阵列装置。混合计数器阵列包括包括N个计数器装置的第一计数器部分，每个计数器装置用于接收表示来自事件源的事件发生的信号，并提供对应于混合计数器阵列的较低位的第一计数值。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示混合计数器阵列的较高阶位的第二计数值。控制装置监视第一计数器部分的N个计数器装置中的每一个，并且启动更新存储在第二计数器部分中相应的可寻址存储器位置处的对应的第二计数值的值。因此，第一和第二计数值的组合提供了接收事件数量的瞬时量度。

86. 发明申请

US20090116611A1 SPACE AND POWER EFFICIENT HYBRID COUNTERS ARRAY 失效
标题翻译：空间和功率有效的混合计数器阵列
公开(公告)号：US20090116611A1
公开(公告)日：2009-05-07
申请号：US12120416
申请日：2008-05-14
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G06M3/00
CPC分类号： H03K21/026
摘要： A hybrid counter array device for counting events. The hybrid counter array includes a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits of the hybrid counter array. A control device monitors each of the N counter devices of the first counter portion and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location in the second counter portion. Thus, a combination of the first and second count values provide an instantaneous measure of number of events received.
摘要翻译：用于计数事件的混合计数器阵列装置。混合计数器阵列包括包括N个计数器装置的第一计数器部分，每个计数器装置用于接收表示来自事件源的事件发生的信号，并提供对应于混合计数器阵列的较低位的第一计数值。混合计数器阵列包括第二计数器部分，其包括具有与N个计数器装置对应的N个可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示混合计数器阵列的较高阶位的第二计数值。控制装置监视第一计数器部分的N个计数器装置中的每一个，并且启动更新存储在第二计数器部分中相应的可寻址存储器位置处的对应的第二计数值的值。因此，第一和第二计数值的组合提供了接收事件数量的瞬时量度。

87. 发明申请

US20090077571A1 METHOD AND APPARATUS FOR EFFICIENT PERFORMANCE MONITORING OF A LARGE NUMBER OF SIMULTANEOUS EVENTS 有权
标题翻译：大量同时活动的有效执行监测方法和装置
公开(公告)号：US20090077571A1
公开(公告)日：2009-03-19
申请号：US12324254
申请日：2008-11-26
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F3/00
CPC分类号： G06F11/348 , Y02D10/34
摘要： A system for monitoring a large number of simultaneous events implements a hybrid counter array device having a first counter portion comprising counter devices, each counter device for receiving signals representing occurrences of events from an event source and providing a first count value corresponding to a lower order bits of the hybrid counter array. A second counter portion comprises a memory array device having addressable memory locations in correspondence with the counter devices, each addressable memory location for storing a second count value representing higher order bits. A control device monitors each of the counter devices and initiates updating a value of a corresponding second count value stored at the corresponding addressable memory location. The system includes interrupt pre-indication for providing fast interrupt trigger to a processor device when a count value related to an event equals a threshold value. A data transfer sub-system additionally enables one or more of: read access or write access to both the count values in the first and second counter portions over a narrow bus, the read/write access for purposes of initializing and determining status of the count values for a monitored event type in response to a processor device request.
摘要翻译：一种用于监视大量同时事件的系统实现了具有包括计数器装置的第一计数器部分的混合计数器阵列装置，每个计数器装置用于接收表示从事件源发生的事件的信号，并提供对应于较低次序的第一计数值混合计数器阵列的位。第二计数器部分包括具有与计数器装置对应的可寻址存储器位置的存储器阵列器件，每个可寻址存储器位置用于存储表示较高阶位的第二计数值。控制装置监视每个计数器装置并且启动更新存储在相应的可寻址存储器位置处的对应的第二计数值的值。当与事件相关的计数值等于阈值时，该系统包括用于向处理器设备提供快速中断触发的中断预指示。数据传输子系统另外启用以下一个或多个：通过窄总线对第一和第二计数器部分中的计数值进行读访问或写入访问，用于初始化和确定计数状态的读/写访问响应于处理器设备请求的被监视事件类型的值。

88. 发明授权

US07404041B2 Low complexity speculative multithreading system based on unmodified microprocessor core 失效
标题翻译：基于未修改的微处理器核心的低复杂度推测性多线程系统
公开(公告)号：US07404041B2
公开(公告)日：2008-07-22
申请号：US11351830
申请日：2006-02-10
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3828 , G06F9/3842 , G06F9/3851 , G06F12/0815 , G06F2212/507
摘要： A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持线程级推测性执行的系统，方法和计算机程序产品，该处理单元适于以推测和非推测模式并行执行线程。每个处理单元包括与其可操作地连接的高速缓存的高速缓冲存储器层级。该装置包括仅在线程级推测模式中使用的每个处理单元本地的附加高速缓存级别，每个附加高速缓存用于存储推测结果以及处理推测性线程时与其相关联的处理器相关联的状态。在每个处理单元处的附加本地高速缓存级别互连，使得推测值和控制数据可以在并行执行线程之间转发。提供了一种控制实现，其实现在计算环境中执行的推测线程之间的推测性一致性。

89. 发明申请

US20080126634A1 Method and apparatus for updating wide storage array over a narrow bus 有权
标题翻译：用于在窄总线上更新宽存储阵列的方法和装置
公开(公告)号：US20080126634A1
公开(公告)日：2008-05-29
申请号：US11507306
申请日：2006-08-21
申请人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
发明人： Alan G. Gara , Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F13/38
CPC分类号： G06F13/4018 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for transferring wide data (e.g., n bits) from a narrow bus (m bits, where m
摘要翻译：一种用于从窄总线（m位，其中m

90. 发明授权

US07330996B2 Twin-tailed fail-over for fileservers maintaining full performance in the presence of a failure 有权
标题翻译：文件服务器的双尾故障转移在出现故障时保持全面的性能
公开(公告)号：US07330996B2
公开(公告)日：2008-02-12
申请号：US10468990
申请日：2002-02-25
申请人： Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow
发明人： Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method for maintaining full performance of a file system in the presence of a failure is provided. The file system having N storage devices, where N is an integer greater than zero and N primary file servers where each file server is operatively connected to a corresponding storage device for accessing files therein. The file system further having a secondary file server operatively connected to at least one of the N storage devices. The method including: switching the connection of one of the N storage devices to the secondary file server upon a failure of one of the N primary file servers; and switching the connections of one or more of the remaining storage devices to a primary file server other than the failed file server as necessary so as to prevent a loss in performance and to provide each storage device with an operating file server.
摘要翻译：提供了在出现故障的情况下维持文件系统的完整性能的方法。具有N个存储设备的文件系统，其中N是大于零的整数，N个主文件服务器，其中每个文件服务器可操作地连接到用于访问其中的文件的相应存储设备。所述文件系统还具有可操作地连接到所述N个存储设备中的至少一个的辅助文件服务器。该方法包括：在N个主要文件服务器之一发生故障时，将N个存储设备之一的连接切换到次要文件服务器; 并且根据需要将一个或多个剩余存储设备的连接切换到除故障文件服务器之外的主文件服务器，以防止性能损失并向每个存储设备提供操作文件服务器。

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