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81. 发明申请

US20050264341A1 Semiconductor switch 失效
标题翻译：半导体开关
公开(公告)号：US20050264341A1
公开(公告)日：2005-12-01
申请号：US11138474
申请日：2005-05-27
申请人： Masahiro Hikita , Manabu Yanagihara , Daisuke Ueda
发明人： Masahiro Hikita , Manabu Yanagihara , Daisuke Ueda
IPC分类号： H01P1/15 , H03K17/06 , H03K17/687 , H04B1/44
CPC分类号： H03K17/6871 , H03K17/063
摘要： The present invention, which aims at providing a semiconductor switch capable of reducing harmonic distortion, is made up of: an input terminal 101; an output terminal 102; a through FET 106 that is connected serially to the signal path between the input terminal 101 and the output terminal 102; a shunt FET 107 that is connected in between the output terminal 102 and the ground; and a distortion reducing circuit 120 that is connected in parallel with the through FET 106. In this semiconductor switch, the distortion reducing circuit 120 includes: a first diode 109 and a second diode 110 that are placed in parallel with each other; a first constant voltage source 111 and a second constant voltage source 112 that are placed in parallel with each other; and a FET 108.
摘要翻译：旨在提供能够减少谐波失真的半导体开关的本发明由输入端子101构成，输出端子102; 与输入端子101和输出端子102之间的信号路径串联连接的贯通FET106; 连接在输出端子102和地之间的并联FET107; 以及与通过FET 106并联连接的失真减小电路120。在该半导体开关中，失真减少电路120包括：彼此平行放置的第一二极管109和第二二极管110; 彼此平行放置的第一恒定电压源111和第二恒定电压源112; 和FET 108。

82. 发明申请

US20050151208A1 Semiconductor switch 有权
标题翻译：半导体开关
公开(公告)号：US20050151208A1
公开(公告)日：2005-07-14
申请号：US11022814
申请日：2004-12-28
申请人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
发明人： Takashi Uno , Manabu Yanagihara , Hidetoshi Ishida , Tsuyoshi Tanaka
IPC分类号： H01L27/095 , H01L27/12 , H01L29/812 , H01L21/336 , H01L29/94
CPC分类号： H01L27/1203 , H01L29/8126
摘要： In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.
摘要翻译：在本发明的半导体开关中，栅电极，源电极和漏极形成为使得MESFET的栅极和漏极之间的距离（假设分流FET）比栅极和漏极之间的距离长假定通过FET，MESFET的假定为通过FET的MESFET的栅极击穿电压在不改变MESFET的栅极击穿电压的情况下增加，并且假定为通过FET，所以增加了MESFET的栅极击穿电压。

83. 发明授权

US06852580B2 Method of fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06852580B2
公开(公告)日：2005-02-08
申请号：US10150326
申请日：2002-05-20
申请人： Manabu Yanagihara , Tsuyoshi Tanaka , Akihisa Sugimura
发明人： Manabu Yanagihara , Tsuyoshi Tanaka , Akihisa Sugimura
IPC分类号： H01L21/328 , G05F3/20 , H03F1/30 , H01L21/338
CPC分类号： H03F1/302 , G05F3/205
摘要： The invention provides a bias circuit for suppressing change with temperature of an idle current of a power transistor and a semiconductor device including the bias circuit. The bias circuit includes a first bipolar transistor having an emitter, a base and a collector, and at least one Schottky diode connected to the base of the first bipolar transistor, and the at least one Schottky diode is provided for supplying a base potential for suppressing a collector current of the first bipolar transistor from changing in accordance with temperature change.
摘要翻译：本发明提供一种用于抑制功率晶体管的空载电流随温度变化的偏置电路和包括该偏置电路的半导体器件。偏置电路包括具有发射极，基极和集电极的第一双极晶体管和连接到第一双极晶体管的基极的至少一个肖特基二极管，并且提供至少一个肖特基二极管以提供用于抑制的基极电位第一双极晶体管的集电极电流根据温度变化而变化。

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