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81. 发明授权

US06353326B2 Test carrier with molded interconnect for testing semiconductor components 失效
标题翻译：带有模拟互连的测试载体，用于测试半导体元件
公开(公告)号：US06353326B2
公开(公告)日：2002-03-05
申请号：US09143300
申请日：1998-08-28
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , John O. Jacobson , James M. Wark , Syed Sajid Ahmad
IPC分类号： G01R3102
CPC分类号： G01R1/0483
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for fabricating the carrier are provided. The carrier includes a molded plastic base, a lead frame, and an interconnect. The interconnect includes contacts for making temporary electrical connections with corresponding contacts (e.g., bond pads, solder balls) on the components. The carrier is fabricated by attaching the interconnect to the lead frame, and then molding the plastic base to the interconnect and lead frame. An alternate embodiment carrier includes a board to which multiple interconnects are molded or laminated. In addition, clip members retain the components on the board in electrical communication with the interconnects.
摘要翻译：提供了用于测试半导体部件的半导体载体，例如裸芯片和芯片级封装，以及制造载体的方法。载体包括模制塑料基底，引线框架和互连件。互连件包括用于与组件上的相应触点（例如，接合焊盘，焊球）进行临时电连接的触点。通过将互连件附接到引线框架，然后将塑料基底模制到互连和引线框架来制造载体。替代实施例的载体包括多个互连件模制或层压的板。另外，夹子构件保持电路板上与组件电连通的组件。

82. 发明授权

US06246245B1 Probe card, test method and test system for semiconductor wafers 失效
标题翻译：半导体晶圆的探针卡，测试方法和测试系统
公开(公告)号：US06246245B1
公开(公告)日：2001-06-12
申请号：US09027880
申请日：1998-02-23
申请人： Salman Akram , C. Patrick Doherty , Warren M. Farnworth , David R. Hembree
发明人： Salman Akram , C. Patrick Doherty , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , G01R1/07378
摘要： A probe card for testing a semiconductor wafer, a test method, and a test system employing the probe card are provided. The probe card includes: a substrate; patterns of pin contacts slidably mounted to the substrate; and a force applying member for biasing the pin contacts into electrical contact with die contacts on the wafer. In an illustrative embodiment the force applying member includes spring loaded electrical connectors in physical and electrical contact with the pin contacts. Alternately, the force applying member includes a compressible pad for multiple pin contacts, or separate compressible pads for each pin contact. A penetration depth of the pin contacts into the die contacts is controlled by selecting a spring force of the force applying member, and an amount of Z-direction overdrive of the pin contacts into the die contacts.
摘要翻译：提供了用于测试半导体晶片的探针卡，测试方法和采用探针卡的测试系统。探针卡包括：基底; 引脚触点的图案可滑动地安装到基板上; 以及用于使所述销触点偏压以与所述晶片上的芯片触点电接触的施力部件。在示例性实施例中，施力构件包括与销触点物理和电接触的弹簧加载的电连接器。或者，施力构件包括用于多个针接触的可压缩垫，或者每个销接触的单独的可压缩垫。通过选择力施加部件的弹簧力来控制销接触到模具接触部中的穿透深度，并且销的Z方向过驱动量接触到模具接触件中。

83. 发明授权

US6060894A Temporary package, method and system for testing semiconductor dice having backside electrodes 有权
标题翻译：用于测试具有背面电极的半导体裸片的临时封装，方法和系统
公开(公告)号：US6060894A
公开(公告)日：2000-05-09
申请号：US365676
申请日：1999-08-02
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , James M. Wark
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , James M. Wark
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2886
摘要： A temporary package, a method, and a system for testing a semiconductor die having a backside electrode are provided. The temporary package includes a base for retaining the die; a conductive member for electrically contacting the backside electrode on the die; and terminal contacts in electrical communication with the conductive member. The package also includes a force applying mechanism for biasing the conductive member against the backside electrode. A conductive path between the conductive member and terminal contacts can be through a wire, or through the force applying mechanism. In an alternate embodiment the temporary package includes a base and terminal contacts formed in the configuration of a conventional semiconductor package. A cover for the base can include a metal, carbon filled elastomer, conductive foam, or conductive adhesive conductive member. The conductive member can be adapted to simultaneously contact the backside electrode on the die, and a mating contact on the base in electrical communication with the terminal contact. In addition, the conductive member can function as a heat sink for cooling the die during the test procedures.
摘要翻译：提供了一种用于测试具有背面电极的半导体管芯的临时封装，方法和系统。临时包装包括用于保持模具的基座; 导电构件，用于电接触模具上的背面电极; 以及与导电构件电连通的端子触点。封装还包括用于将导电构件偏压抵靠背侧电极的施力机构。导电构件和端子触点之间的导电路径可以通过导线或通过施力机构。在替代实施例中，临时封装包括以常规半导体封装的结构形成的基极和端子触点。用于基座的盖可以包括金属，填充碳的弹性体，导电泡沫或导电粘合剂导电构件。导电构件可以适于同时接触模具上的背面电极，以及基座上与端子触点电连通的配合触点。此外，导电构件可以用作在测试过程中用于冷却模具的散热器。

84. 发明授权

US6025731A Hybrid interconnect and system for testing semiconductor dice 失效
标题翻译：混合互连和半导体骰子测试系统
公开(公告)号：US6025731A
公开(公告)日：2000-02-15
申请号：US821468
申请日：1997-03-21
申请人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , James M. Wark , Derek Gochnour
发明人： David R. Hembree , Salman Akram , Warren M. Farnworth , Alan G. Wood , James M. Wark , Derek Gochnour
IPC分类号： G01R1/04 , G01R1/073 , G01R1/73
CPC分类号： G01R1/0466 , G01R1/0735
摘要： An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact members, configured to electrically contact corresponding contact locations on the die. The interconnect also includes a pattern of conductors formed separately from the substrate, and then bonded to the substrate, in electrical communication with the contact members. The conductors can be mounted to a multi layered tape similar to TAB tape, or alternately bonded directly to the substrate. In addition, each conductor can include an opening aligned with a corresponding contact member, and filled with a conductive material, such as a conductive adhesive or solder. The conductive material electrically connects the contact members and conductors, and provides an expansion joint to allow expansion of the conductors without stressing the contact members. Also provided are a system for testing dice that includes the interconnect, and a system for testing wafers wherein the interconnect is formed as a probe card.
摘要翻译：提供用于与半导体管芯进行电连接的互连。互连包括具有整体形成的接触构件的基板，其构造成电接触管芯上相应的接触位置。互连还包括与衬底分开形成的导体图案，然后与接触构件电气连接到衬底。导体可以安装到类似于TAB带的多层胶带上，或者可以直接粘合到基底上。此外，每个导体可以包括与对应的接触构件对准的开口，并且填充有诸如导电粘合剂或焊料的导电材料。导电材料电连接接触构件和导体，并且提供膨胀接头以允许导体的膨胀而不会压紧接触构件。还提供了一种用于测试包括互连的骰子的系统，以及用于测试晶片的系统，其中互连形成为探针卡。

85. 发明授权

US5949242A Method and apparatus for testing unpackaged semiconductor dice 失效
标题翻译：用于测试未封装的半导体骰子的方法和装置
公开(公告)号：US5949242A
公开(公告)日：1999-09-07
申请号：US657854
申请日：1996-05-31
申请人： Alan G. Wood , Warren M. Farnworth , Salman Akram , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , Salman Akram , David R. Hembree
IPC分类号： G01R31/26 , G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： G01R1/07314 , G01R1/0433 , G01R1/0483 , G01R31/2886 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R1/0466 , G01R3/00 , G01R31/2863 , G01R31/2889 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A method and apparatus for testing unpackaged semiconductor dice includes a mother board and a plurality of interconnects mounted on the mother board and adapted to establish a temporary electrical connection with the dice. The interconnects can be formed with a silicon substrate and raised contact members for contacting the bond pads of a die. Alternately the interconnects can be formed with micro bump contact members mounted on an insulating film. The mother board allows each die to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board includes interconnects that allow the dice to be tested individually for speed and functionality. Multiple daughter boards can then be mounted to the mother board for burn-in testing using standard burn-in ovens.
摘要翻译：用于测试未封装半导体晶片的方法和装置包括安装在母板上的母板和多个互连件，并且适于与裸片建立临时电连接。互连可以形成有硅衬底和用于接触管芯的接合焊盘的凸起的接触构件。或者，互连可以由安装在绝缘膜上的微凸块接触构件形成。母板允许每个模具分别测试速度和功能，并且还可以使用标准烧录炉并行测试。在替代实施例中，使用母板/子板布置进行测试。每个子板包括互连，允许骰子单独测试速度和功能。然后可以将多个子板安装到母板上，以使用标准老化炉进行老化测试。

86. 发明授权

US06735855B2 Methods for electrical connector 失效
标题翻译：电连接器方法
公开(公告)号：US06735855B2
公开(公告)日：2004-05-18
申请号：US10121176
申请日：2002-04-11
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth
IPC分类号： H05K330
CPC分类号： H01R13/2421 , G01R1/0466 , G01R1/0483 , H01L2924/0002 , H01R12/714 , H01R2201/20 , H05K7/1061 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49139 , Y10T29/4914 , Y10T29/49144 , Y10T29/49149 , Y10T29/49151 , Y10T29/49153 , Y10T29/49155 , Y10T29/49165 , Y10T29/49174 , Y10T29/49204 , Y10T29/49222 , Y10T29/49224 , Y10T29/53174 , H01L2924/00
摘要： In a socket to test semiconductor die, a recessed socket contact that avoids pinching the die contacts is diclosed. The socket contacts allow for smaller socket holes and, allow denser contact spacing. A variety of embodiments are presented that are suitable for use depending on the spacing between the conducters. For more closely spaced conductors, the body of the socket contact comprises a head, a spring coupled to the head, and a shaft coupled to the spring. No outer shell is needed for the spring, as the nonconductive sides of the socket hole serve that function. For conductors spaced further apart, the body of the socket contact comprises a metal shaft having an aperture. Compression causes the shaft to close around the slit, thereby decreasing the amount of lateral buckling. For even more densly spaced contacts, semiconductor fabrication techniques are used to construct a dense array of contacts.
摘要翻译：在用于测试半导体管芯的插座中，隐藏了避免挤压模具触头的凹入插座触点。插座触点允许更小的插座孔，并允许更密集的接触间距。呈现出根据导体之间的间距适合使用的各种实施例。对于更紧密间隔的导体，插座触头的主体包括头部，联接到头部的弹簧和联接到弹簧的轴。弹簧不需要外壳，因为插座孔的不导电侧面具有这种功能。对于间隔更远的导体，插座触头的主体包括具有孔的金属轴。压缩使轴在缝隙周围闭合，从而减少侧向屈曲的量。对于更密集间隔的触点，使用半导体制造技术来构造密集的触点阵列。

87. 发明授权

US06420892B1 Calibration target for calibrating semiconductor wafer test systems 有权
标题翻译：用于校准半导体晶圆测试系统的校准目标
公开(公告)号：US06420892B1
公开(公告)日：2002-07-16
申请号：US09685132
申请日：2000-10-10
申请人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
发明人： Andrew J. Krivy , Warren M. Farnworth , David R. Hembree , Salman Akram , James M. Wark , John O. Jacobson
IPC分类号： G01R3102
CPC分类号： G01R35/005 , G01R1/073 , Y10T29/49197
摘要： A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.
摘要翻译：提供了用于校准包括探针测试仪和探针卡分析仪在内的半导体晶片测试系统的校准目标。还提供了使用校准目标的校准方法以及用于制造校准目标的方法。校准目标包括其上形成有各种三维对准特征的基板。第一类型的对准特征包括形成在其顶端部分上的对比层和对准基准。对比层和对准基准被配置为通过探针卡分析仪或测试系统的观察装置进行观察，以实现X方向和Y方向校准。第二类型的对准特征包括形成在其尖端部分上的导电层，其被配置为与探针卡分析器的支撑板上的触点或测试系统的探针卡上的探针接触电接合，以实现 Z方向校准。对准特征可以通过在硅衬底上形成凸起构件，以及在凸起构件上沉积和蚀刻金属层来形成。

88. 发明授权

US06407570B1 Interconnect for testing semiconductor components having support members for preventing component flexure 失效
标题翻译：用于测试具有用于防止部件挠曲的支撑构件的半导体部件的互连
公开(公告)号：US06407570B1
公开(公告)日：2002-06-18
申请号：US09479894
申请日：2000-01-18
申请人： Warren M. Farnworth , Mike Hess , David R. Hembree , James M. Wark , John O. Jacobson , Salman Akram
发明人： Warren M. Farnworth , Mike Hess , David R. Hembree , James M. Wark , John O. Jacobson , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0483 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165
摘要： A test carrier and an interconnect for testing semiconductor components, such as bare dice and chip scale packages, are provided. The carrier includes a base on which the interconnect is mounted, and a force applying mechanism for biasing the component against the interconnect. The interconnect includes interconnect contacts configured to make temporary electrical connections with component contacts (e.g., bond pads, solder balls). The interconnect also includes support members configured to physically contact the component, to prevent flexure of the component due to pressure exerted by the force applying mechanism. The support members can be formed integrally with the interconnect using an etching process. In addition, the support members can include an elastomeric layer to provide cushioning and to accommodate Z-direction dimensional variations.
摘要翻译：提供了测试载体和用于测试半导体部件（例如裸芯片和芯片级封装）的互连。载体包括其上安装有互连件的基座，以及用于将部件抵靠互连件的力施加机构。互连包括被配置为与部件触点（例如，焊盘，焊球）进行临时电连接的互连触头。互连还包括被配置为物理地接触部件的支撑部件，以防止部件由于施力机构施加的压力而挠曲。支撑构件可以使用蚀刻工艺与互连一体地形成。此外，支撑构件可以包括弹性体层以提供缓冲并适应Z方向尺寸变化。

89. 发明授权

US06407451B2 Micromachined chip scale package 失效
标题翻译：微加工芯片级封装
公开(公告)号：US06407451B2
公开(公告)日：2002-06-18
申请号：US09769983
申请日：2001-01-25
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth
IPC分类号： H01L2304
CPC分类号： H01L23/13 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05147 , H01L2224/05171 , H01L2224/05647 , H01L2224/1148 , H01L2224/13099 , H01L2224/131 , H01L2224/1319 , H01L2224/13339 , H01L2224/16237 , H01L2924/0001 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2224/29099 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2924/013
摘要： A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface is disclosed. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array, or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.
摘要翻译：公开了一种芯片级封装，其由具有层压到其有源表面上的硅片的半导体管芯组成。模具的接合焊盘通过微机械加工通过坯件的孔进入。该封装可以与引线接合使用，或者可以将焊料或其它导电凸块放置在用于倒装芯片应用的空白孔中。此外，封装可以用于将管芯的外部连接重新路由到其他位置，例如集中式球栅阵列，或用于直接或离散管芯连接（DDC）到载体的边缘连接装置。优选的是，芯片级封装形成在晶片级，作为如此形成的多个封装之一，其形成有晶片级坯料，并且整个晶片被烧入并测试以识别已知的良好裸片（KGD ），然后将晶片层压板分离成单个包装。

90. 发明授权

US06400174B2 Test system having alignment member for aligning semiconductor components 失效
公开(公告)号：US06400174B2
公开(公告)日：2002-06-04
申请号：US09749173
申请日：2000-12-27
申请人： Salman Akram , Warren M. Farnworth , Michael E. Hess , David R. Hembree
发明人： Salman Akram , Warren M. Farnworth , Michael E. Hess , David R. Hembree
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , G01R31/2886 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/8592 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/10157 , H01L2924/10253 , H01L2924/15312 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A test system for testing semiconductor components includes an interconnect having contacts for making temporary electrical connections with terminal contacts on the components. The interconnect contacts can be configured to electrically engage planar terminal contacts (e.g., bond pads, test pads) or bumped terminal contacts (e.g., solder bumps, solder balls) on the components. The test system also includes an alignment member for aligning the components to the interconnect. Different embodiments of the alignment member include: a curable polymer material molded in place on the interconnect; an alignment opening formed as an etched pocket in a substrate of the interconnect; and a separate fence attached to the interconnect using an alignment fixture.

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