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    • 81. 发明申请
    • Card connector
    • 卡连接器
    • US20080207060A1
    • 2008-08-28
    • US11878400
    • 2007-07-24
    • Koichi KiryuHideo Miyazawa
    • Koichi KiryuHideo Miyazawa
    • H01R33/00
    • H01R27/00H01R13/64
    • A card connector is disclosed that includes a housing for accommodating a first card, a second card, and a third card; a first contact member arranged to be connected to the first card; a second contact member arranged to be connected to the second card, which has a larger width than the first card and a smaller thickness than the first card; a third contact member arranged to be connected to the third card, which has a smaller width than the first and second card and a smaller thickness than the first and second card; and a connection control mechanism that selectively connects one of the first card, the second card, or the third card. When one of the first card, the second card, or the third card is connected, the connection control mechanism prevents the other cards from being connected.
    • 公开了一种卡连接器,其包括用于容纳第一卡,第二卡和第三卡的外壳; 布置成连接到所述第一卡的第一接触构件; 布置成连接到第二卡的第二接触构件,其具有比第一卡大的宽度和比第一卡片更小的厚度; 布置成连接到第三卡的第三接触构件,其具有比第一卡和第二卡小的宽度,并且具有比第一卡和第二卡更小的厚度; 以及连接控制机构,其选择性地连接第一卡,第二卡或第三卡中的一个。 当第一卡,第二卡或第三卡之一连接时,连接控制机构防止其他卡连接。
    • 82. 发明申请
    • Data decoding method and data decoding device employing same
    • 数据解码方法和数据解码装置
    • US20080137724A1
    • 2008-06-12
    • US12003940
    • 2008-01-03
    • Yoshinori TanakaHideo Miyazawa
    • Yoshinori TanakaHideo Miyazawa
    • H03K9/08H03M13/00G06F11/00
    • H04L1/0045G06K7/0008H04B5/0031H04B5/0062H04L25/4904
    • A data decoding method judges a signal state where there is a transition from a low level to a high level or from a high level to a low level at the center portion of a bit interval as logical “1” or “0”, and a signal state where a low level continues or a high level continues over the entire bit interval as logical “0” or “1”. The method has the steps of: measuring a first time duration in which the bit series signal transitions from a low level to the next low level, measuring a second time duration in which the bit series signal transitions from a high level to the next high level, and deciding a logical “0” or “1” value for the target bit to be decided based on the combination of the first time duration and the second time duration measured for the target bit.
    • 数据解码方法判断在比特间隔的中心部分处于从低电平到高电平或从高电平到低电平的信号状态,作为逻辑“1”或“0”,并且 低电平持续的信号状态或高电平在整个位间隔上持续为逻辑“0”或“1”。 该方法具有以下步骤:测量比特串行信号从低电平转换到下一个低电平的第一持续时间,测量比特串行信号从高电平转换到下一个高电平的第二持续时间 并且基于针对所述目标位测量的所述第一持续时间和所述第二持续时间的组合来确定要确定的所述目标比特的逻辑“0”或“1”值。