专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

81. 发明申请

US20090032959A1 ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS 失效
标题翻译：具有分层尺寸的电熔丝和电阻
公开(公告)号：US20090032959A1
公开(公告)日：2009-02-05
申请号：US11831236
申请日：2007-07-31
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

82. 发明授权

US07485508B2 Two-sided semiconductor-on-insulator structures and methods of manufacturing the same 有权
标题翻译：双面绝缘体上半导体结构及其制造方法
公开(公告)号：US07485508B2
公开(公告)日：2009-02-03
申请号：US11627653
申请日：2007-01-26
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L21/338
CPC分类号： H01L27/0694 , H01L21/84 , H01L27/1203
摘要： Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second semiconductor layer and to form second type devices thereupon. Conductive vias may be formed through the buried insulator layer to electrically connect the first type devices and the second type devices. Use of block masks is minimized since each side of the buried insulator has only one type of devices. Two levels of devices are present in the structure and boundary areas between different types of devices are reduced or eliminated, thereby increasing packing density of devices. The same alignment marks may be used to align the wafer either front side up or back side up.
摘要翻译：利用绝缘体上半导体衬底的两侧形成MOSFET结构。在第一半导体层上形成第一类型器件之后，把手晶片结合到第一中间线介电层的顶部。然后移除载体衬底的下部以暴露第二半导体层并在其上形成第二类型器件。可以通过掩埋绝缘体层形成导电孔，以电连接第一类型器件和第二类型器件。掩模掩模的使用最小化，因为埋入绝缘体的每一侧只有一种类型的器件。结构中存在两级装置，减少或消除不同类型装置之间的边界区域，从而提高装置的包装密度。可以使用相同的对准标记来将晶片的前侧向上或向后对准。

83. 发明申请

US20090026543A1 FINFET WITH SUBLITHOGRAPHIC FIN WIDTH 有权
标题翻译： FINFET带子光栅宽度
公开(公告)号：US20090026543A1
公开(公告)日：2009-01-29
申请号：US11828403
申请日：2007-07-26
申请人： Haining S. Yang
发明人： Haining S. Yang
IPC分类号： H01L27/105 , H01L21/8234
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs.
摘要翻译：在半导体层上的绝缘体层中形成具有两个平行边缘的至少一个凹陷区域，使得凹陷区域的长度方向与要形成的鳍状半导体层的半导体层中的半导体材料的最佳载流子迁移率表面重合。自组装嵌段共聚物被施加在所述至少一个凹陷区域内并退火以形成具有亚光刻宽度并包含第一聚合物嵌段组分的一组平行聚合物嵌段体线。使用该组平行聚合物阻挡线作为蚀刻掩模将亚光刻宽度线的图案转移到半导体层中。如此形成的亚光刻宽度半导体鳍片可具有用于p型finFET和n型finFET的最佳载流子迁移率的侧壁。

84. 发明申请

US20090026523A1 PARTIALLY GATED FINFET 有权
标题翻译：部分浇注金属
公开(公告)号：US20090026523A1
公开(公告)日：2009-01-29
申请号：US11782079
申请日：2007-07-24
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/785
摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.
摘要翻译：在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

85. 发明申请

US20080311714A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 失效
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080311714A1
公开(公告)日：2008-12-18
申请号：US11761466
申请日：2007-06-12
申请人： Bruce B. Doris , Thomas W. Dyer , Haining S. Yang
发明人： Bruce B. Doris , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823878 , H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A complimentary metal oxide semiconductor and a method of manufacturing the same using a self-aligning process to form one of the stacks of device. The method includes depositing an oxide layer over a portion of a metal layer over an nFET region of a CMOS structure and etching the metal layer over a pFET region of the CMOS structure. The method further includes etching at the oxide layer over the nFET region and forming gate structures over the nFET region and pFET region.
摘要翻译：互补的金属氧化物半导体及其制造方法使用自对准工艺来形成器件堆叠之一。该方法包括在CMOS结构的nFET区域上的金属层的一部分上沉积氧化物层，并在CMOS结构的pFET区域上蚀刻金属层。该方法还包括在nFET区域上的氧化物层处蚀刻并在nFET区域和pFET区域上形成栅极结构。

86. 发明授权

US07462915B2 Method and apparatus for increase strain effect in a transistor channel 有权
标题翻译：在晶体管通道中增加应变效应的方法和装置
公开(公告)号：US07462915B2
公开(公告)日：2008-12-09
申请号：US11467446
申请日：2006-08-25
申请人： Haining S. Yang , Huilong Zhu
发明人： Haining S. Yang , Huilong Zhu
IPC分类号： H01L29/94
CPC分类号： H01L29/6653 , H01L29/66545 , H01L29/7842
摘要： A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.
摘要翻译：提供了具有增强应力的晶体管沟道的半导体器件。为了实现增强的应力晶体管沟道，在栅极堆叠的一部分上，在器件衬底上优先形成氮化物膜，几乎没有氮化物。氮化物膜可以优选仅在非保形层中沉积在硅衬底上，其中在栅堆叠的上部上沉积很少至无氮化物。氮化物膜也可以均匀地沉积在保形层上的硅衬底和栅极堆叠上，其中靠近栅极堆叠的上部区域的氮化物膜在稍后的步骤中优先被去除。在一些实施例中，通过去除栅极堆叠的上部来去除靠近栅极堆叠顶部的氮化物。在任何方法中，通过使沉积在栅极堆叠上的氮化物最小化，同时在衬底上沉积氮化物来增强晶体管沟道中的应力。

87. 发明申请

US20080290413A1 SOI MOSFET WITH A METAL SEMICONDUCTOR ALLOY GATE-TO-BODY BRIDGE 审中-公开
标题翻译：具有金属半导体合金栅极至体电桥的SOI MOSFET
公开(公告)号：US20080290413A1
公开(公告)日：2008-11-27
申请号：US11751222
申请日：2007-05-21
申请人： Jack A. Mandelman , Haining S. Yang
发明人： Jack A. Mandelman , Haining S. Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/78615
摘要： A body contact region is formed in a portion of the active region. A gate dielectric and a gate conductor layer are formed on the active region and patterned to define a gate electrode. A portion of the gate electrode is removed to expose a top surface of the body contact region adjoining a sidewall of the gate dielectric which adjoins a sidewall of the gate conductor. A substrate metal semiconductor alloy is formed on the top surface of the body contact region, and a gate metal semiconductor alloy is formed on the sidewall of the gate conductor. The substrate metal semiconductor alloy and the gate metal semiconductor alloy are adjoined during formation, providing a gate-to-body bridge of a MOSFET formed on the active region.
摘要翻译：在有源区域的一部分中形成体接触区域。栅极电介质和栅极导体层形成在有源区上并被图案化以限定栅电极。栅电极的一部分被去除以暴露邻接栅极电介质的与栅极导体的侧壁相邻的侧壁的本体接触区域的顶表面。衬底金属半导体合金形成在本体接触区域的顶表面上，栅极金属半导体合金形成在栅极导体的侧壁上。衬底金属半导体合金和栅极金属半导体合金在形成期间相邻，提供形成在有源区上的MOSFET的栅对体桥。

88. 发明申请

US20080283930A1 EXTENDED DEPTH INTER-WELL ISOLATION STRUCTURE 审中-公开
标题翻译：延长的深度隔离隔离结构
公开(公告)号：US20080283930A1
公开(公告)日：2008-11-20
申请号：US11748528
申请日：2007-05-15
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/76229 , H01L21/76232
摘要： By depositing and forming a spacer out of a semiconductor material layer or a dielectric material layer on the edges of an inter-well isolation area while forming a plug over an intra-well isolation area, a narrow intra-well isolation trench having a normal depth is formed in the intra-well isolation area, while a wider inter-well isolation trench having an extended portion is formed in the inter-well isolation area. The extended portion of the inter-well isolation trench provides enhanced inter-well isolation due to the presence of the extended portion beneath the normal depth. The extended portion of the inter-well isolation trench enables reduction of the width of the intra-well isolation trench structure relative to prior art inter-well isolation structures having a normal depth.
摘要翻译：通过在阱间隔离区域的边缘上沉积和形成间隔物离开半导体材料层或介电材料层，同时在孔内隔离区域上形成插塞，具有正常深度的窄的孔内隔离沟槽形成在井内隔离区域中，而在隔间隔离区域中形成具有延伸部分的更宽的阱间隔离沟槽。由于在正常深度之下存在延伸部分，间隙隔离沟槽的延伸部分提供了增强的井间隔离。相对于具有正常深度的现有技术的间隔间隔离结构，阱间隔离沟槽的延伸部分能够减小井下隔离沟槽结构的宽度。

89. 发明申请

US20080283824A1 METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES 有权
标题翻译：用于形成CMOS器件的应变SI的方法和结构
公开(公告)号：US20080283824A1
公开(公告)日：2008-11-20
申请号：US12173642
申请日：2008-07-15
申请人： An L. STEEGEN , Haining S. Yang , Ying Zhang
发明人： An L. STEEGEN , Haining S. Yang , Ying Zhang
IPC分类号： H01L29/778
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02658 , H01L21/26506 , H01L21/76224 , H01L21/76232 , H01L21/76283 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/665 , H01L29/66575 , H01L29/78 , H01L29/7842 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The strain layer is formed only under at least one of a source region and a drain region of the semiconductor device.
摘要翻译：半导体器件包括具有在半导体衬底的一部分下延伸的至少一个间隙的半导体衬底。栅极堆叠在半导体衬底上。应变层形成在至少一个间隙的至少一部分中。应变层仅形成在半导体器件的源极区域和漏极区域中的至少一个之下。

90. 发明申请

US20080237786A1 NON-PLANAR FUSE STRUCTURE INCLUDING ANGULAR BEND AND METHOD FOR FABRICATION THEREOF 失效
标题翻译：非平面保险丝结构，包括角度弯曲及其制造方法
公开(公告)号：US20080237786A1
公开(公告)日：2008-10-02
申请号：US11693041
申请日：2007-03-29
申请人： Haining S. Yang , Wai-Kin Li , Deok-Kee Kim
发明人： Haining S. Yang , Wai-Kin Li , Deok-Kee Kim
IPC分类号： H01L29/00 , H01L21/326
CPC分类号： H01L23/5256 , H01L29/785 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer.
摘要翻译：熔丝结构包括通常位于衬底内并且复制衬底内的形貌特征的非平面熔断体材料层。非平面熔断体材料层包括有助于在非平面熔断体材料层内提供较低切断电流的角弯曲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式