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81. 发明授权

US08796128B2 Dual metal fill and dual threshold voltage for replacement gate metal devices 有权
标题翻译：用于更换栅极金属器件的双金属填充和双阈值电压
公开(公告)号：US08796128B2
公开(公告)日：2014-08-05
申请号：US13367419
申请日：2012-02-07
申请人： Lisa F. Edge , Nathaniel Berliner , James John Demarest , Balasubramanian S. Haran , Raymond J. Donohue
发明人： Lisa F. Edge , Nathaniel Berliner , James John Demarest , Balasubramanian S. Haran , Raymond J. Donohue
IPC分类号： H01L21/28 , H01L27/088
CPC分类号： H01L29/49 , H01L21/28088 , H01L21/82345 , H01L21/823842 , H01L27/088 , H01L29/66545
摘要： A structure and method for forming a dual metal fill and dual threshold voltage for replacement gate metal devices is disclosed. A selective deposition process involving titanium and aluminum is used to allow formation of two adjacent transistors with different fill metals and different workfunction metals, enabling different threshold voltages in the adjacent transistors.
摘要翻译：公开了用于形成双金属填充物的结构和方法以及用于替换栅极金属器件的双阈值电压。使用涉及钛和铝的选择性沉积方法来形成具有不同填充金属和不同功函数金属的两个相邻晶体管，从而能够在相邻晶体管中实现不同的阈值电压。

82. 发明授权

US08790991B2 Method and structure for shallow trench isolation to mitigate active shorts 有权
标题翻译：浅沟槽隔离的方法和结构，以减轻主动短裤
公开(公告)号：US08790991B2
公开(公告)日：2014-07-29
申请号：US13011546
申请日：2011-01-21
申请人： Jason E. Cummings , Balasubramanian S. Haran , Hemanth Jagannathan , Sanjay Mehta
发明人： Jason E. Cummings , Balasubramanian S. Haran , Hemanth Jagannathan , Sanjay Mehta
IPC分类号： H01L21/76 , H01L21/762 , H01L21/02 , H01L21/8234 , H01L29/06
CPC分类号： H01L21/76224 , H01L21/02107 , H01L21/823481 , H01L21/823878 , H01L29/0649 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.
摘要翻译：提供浅沟槽隔离区域，其中空隙形成基本上或完全从其中消除。浅沟槽隔离减轻半导体衬底的两个有源区域之间的有源短路。浅沟槽隔离区域包括存在于形成在半导体衬底中的沟槽的侧壁和底壁上的双层衬垫。本公开的双层衬垫包括从底部到顶部的浅沟槽隔离衬垫，例如半导体氧化物和/或氮化物，以及高k衬里，例如介电常数大于硅的介电材料氧化物。

83. 发明授权

US08377795B2 Cut first methodology for double exposure double etch integration 有权
标题翻译：切割双曝光双蚀刻集成的第一种方法
公开(公告)号：US08377795B2
公开(公告)日：2013-02-19
申请号：US12698448
申请日：2010-02-02
申请人： Sivananda K. Kanakasabapathy , Veeraraghavan S. Basker , Balasubramanian S. Haran
发明人： Sivananda K. Kanakasabapathy , Veeraraghavan S. Basker , Balasubramanian S. Haran
IPC分类号： H01L21/762 , G03C5/00
CPC分类号： H01L29/4238 , H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/32139
摘要： A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines.
摘要翻译：在半导体结构中形成栅极的多次蚀刻工艺，其中首先形成切割区域，之后形成栅极导体线。

84. 发明申请

US20130026570A1 BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES 有权
公开(公告)号：US20130026570A1
公开(公告)日：2013-01-31
申请号：US13191540
申请日：2011-07-27
申请人： Su Chen Fan , Balasubramanian S. Haran , David V. Horak
发明人： Su Chen Fan , Balasubramanian S. Haran , David V. Horak
IPC分类号： H01L29/772 , H01L23/48 , H01L21/28
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/665 , H01L29/66628 , H01L29/7841 , H01L29/7843 , H01L29/78609
摘要： After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

85. 发明申请

US20130015512A1 LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI 失效
公开(公告)号：US20130015512A1
公开(公告)日：2013-01-17
申请号：US13605260
申请日：2012-09-06
申请人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
发明人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

86. 发明申请

US20130015509A1 LOW RESISTANCE SOURCE AND DRAIN EXTENSIONS FOR ETSOI 失效
标题翻译： ETSOI的低电阻源和漏电延伸
公开(公告)号：US20130015509A1
公开(公告)日：2013-01-17
申请号：US13183666
申请日：2011-07-15
申请人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
发明人： Balasubramanian S. Haran , Hemanth Jagannathan , Sivananda K. Kanakasabapathy , Sanjay Mehta
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/6653 , H01L29/78621
摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.
摘要翻译：在通过各向异性蚀刻共形介电层形成第一栅极间隔物之后对栅极电介质进行构图，以最小化过蚀刻到半导体层中。在一个实施例中，执行选择性外延以顺序地形成凸起的外延半导体部分，一次性栅极间隔物和升高的源极和漏极区域。去除一次性栅极间隔物，并将离子注入进行到隆起的外延半导体部分的暴露部分中以形成源极和漏极延伸区域。在另一个实施例中，用于源极和漏极延伸形成的离子注入在形成第一栅极间隔物的各向异性蚀刻之前通过保形介电层进行。升高的外延半导体部分或构象介电层的存在防止了源极和漏极延伸区域中的半导体材料的完全非晶化，从而使结晶源极和漏极延伸区域再生长。

87. 发明授权

US08232607B2 Borderless contact for replacement gate employing selective deposition 有权
标题翻译：采用选择性沉积的替代栅极的无边界接触
公开(公告)号：US08232607B2
公开(公告)日：2012-07-31
申请号：US12952372
申请日：2010-11-23
申请人： Lisa F. Edge , Balasubramanian S. Haran
发明人： Lisa F. Edge , Balasubramanian S. Haran
IPC分类号： H01L21/02
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823871 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A self-aligned gate cap dielectric can be employed to form a self-aligned contact to a diffusion region, while preventing electrical short with a gate conductor due to overlay variations. In one embodiment, an electroplatable or electrolessly platable metal is selectively deposited on conductive materials in a gate electrode, while the metal is not deposited on dielectric surfaces. The metal portion on top of the gate electrode is converted into a gate cap dielectric including the metal and oxygen. In another embodiment, a self-assembling monolayer is formed on dielectric surfaces, while exposing metallic top surfaces of a gate electrode. A gate cap dielectric including a dielectric oxide is formed on areas not covered by the self-assembling monolayer. The gate cap dielectric functions as an etch-stop structure during formation of a via hole, so that electrical shorting between a contact via structure formed therein and the gate electrode is avoided.
摘要翻译：可以使用自对准栅极帽电介质来形成与扩散区域的自对准接触，同时防止由于覆盖变化导致的栅极导体的电短路。在一个实施例中，可电镀或无电镀的金属被选择性地沉积在栅电极中的导电材料上，同时金属不沉积在电介质表面上。栅极顶部的金属部分被转换成包括金属和氧的栅极电介质。在另一个实施例中，在电介质表面上形成自组装单层，同时暴露栅电极的金属顶表面。在未被自组装单层覆盖的区域上形成包括电介质氧化物的栅极电介质。栅极电介质在形成通孔期间用作蚀刻停止结构，从而避免了在其中形成的接触通孔结构与栅电极之间的电短路。

88. 发明申请

US20120032275A1 METAL SEMICONDUCTOR ALLOY STRUCTURE FOR LOW CONTACT RESISTANCE 失效
公开(公告)号：US20120032275A1
公开(公告)日：2012-02-09
申请号：US12849390
申请日：2010-08-03
申请人： Balasubramanian S. Haran , Sivananda K. Kanakasabapathy
发明人： Balasubramanian S. Haran , Sivananda K. Kanakasabapathy
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76805 , H01L21/76829 , H01L21/76895 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/165 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

89. 发明申请

US20110031503A1 DEVICE WITH STRESSED CHANNEL 审中-公开
标题翻译：具有应力通道的设备
公开(公告)号：US20110031503A1
公开(公告)日：2011-02-10
申请号：US12538627
申请日：2009-08-10
申请人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir S. Adam , Balasubramanian S. Haran
发明人： Bruce B. Doris , Johnathan E. Faltermeier , Lahir S. Adam , Balasubramanian S. Haran
IPC分类号： H01L29/161 , H01L27/092 , H01L21/04 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An FET device is disclosed which contains a source and a drain that are each provided with an extension. The source and the drain, and their extensions, are composed of epitaxial materials containing Ge or C. The epitaxial materials and the Si substrate have differing lattice constants, consequently the source and the drain and their extensions are imparting a state of stress onto the channel. For a PFET device the epitaxial material may be SiGe, or Ge, and the channel may be in a compressive state of stress. For an NFET device the epitaxial material may be SiC and the channel may be in a tensile state of stress. A method for fabricating an FET device is also disclosed. One may form a first recession in the Si substrate to a first depth on opposing sides of the gate. The first recession is filled epitaxially with a first epitaxial material. Then, a second recession may be formed in the Si substrate to a second depth, which is greater than the first depth. Next, one may fill the second recession with a second epitaxial material, which is the same kind of material as the first epitaxial material. The epitaxial materials are selected to have a different lattice constant than the Si substrate, and consequently a state of stress is being imparted onto the channel.
摘要翻译：公开了一种FET器件，其包含各自具有延伸部的源极和漏极。源极和漏极及其延伸部分由包含Ge或C的外延材料组成。外延材料和Si衬底具有不同的晶格常数，因此源极和漏极及其延伸部分在沟道上赋予应力状态。对于PFET器件，外延材料可以是SiGe或Ge，并且沟道可以处于压应力的压缩状态。对于NFET器件，外延材料可以是SiC，并且沟道可以处于应力的拉伸状态。还公开了一种用于制造FET器件的方法。可以在Si衬底中形成第一凹陷到栅极的相对侧上的第一深度。用第一外延材料外延地填充第一次衰退。然后，可以在Si衬底中形成比第一深度更大的第二深度的第二凹陷。接下来，可以用与第一外延材料相同的材料的第二外延材料填充第二凹陷。选择外延材料具有与Si衬底不同的晶格常数，并且因此在沟道上施加应力状态。

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