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81. 发明授权

US06885602B2 Programming method of controlling the amount of write current applied to phase change memory device and write driver circuit therefor 有权
标题翻译：控制施加到相变存储器件的写入电流和写入驱动器电路的编程方法
公开(公告)号：US06885602B2
公开(公告)日：2005-04-26
申请号：US10921797
申请日：2004-08-20
申请人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
发明人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
IPC分类号： G11C13/00 , G11C13/02 , G11C16/02 , H01L27/105 , H01L45/00 , G11C7/04
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0078
摘要： A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the Phase-change Memory (PCM) in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.
摘要翻译：控制施加到相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。编程方法包括保持在较高电阻状态下的PCM的电阻与相位变化存储器（PCM）的电阻在较低电阻状态下的比率恒定或基本上恒定，而与环境温度无关。可以通过增加，减少或保持相同的复位电流和/或设定电流来维持该比率。

82. 发明申请

US20050041464A1 PROGRAMMING METHOD OF CONTROLLING THE AMOUNT OF WRITE CURRENT APPLIED TO PHASE CHANGE MEMORY DEVICE AND WRITE DRIVER CIRCUIT THEREFOR 有权
标题翻译：控制适用于相变存储器件和写驱动电路的写电流量的编程方法
公开(公告)号：US20050041464A1
公开(公告)日：2005-02-24
申请号：US10921797
申请日：2004-08-20
申请人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
发明人： Baek-Hyung Cho , Woo-Yeong Cho , Hyung-Rok Oh , Byung-Gil Choi
IPC分类号： G11C13/00 , G11C13/02 , G11C16/02 , H01L27/105 , H01L45/00 , G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0078
摘要： A programming method which controls the amount of a write current applied to a Phase-change Random Access Memory (PRAM), and a write driver circuit realizing the programming method. The programming method includes maintaining a ratio of a resistance of the PCM in the higher resistance state to a resistance of the PCM in the lower resistance state constant or substantially constant independent of an ambient temperature. The ratio may be maintained by increasing, decreasing, or keeping the same a reset current and/or a set current.
摘要翻译：控制施加到相变随机存取存储器（PRAM）的写入电流的量的编程方法以及实现编程方法的写入驱动器电路。编程方法包括保持PCM在较高电阻状态下的电阻与PCM在较低电阻状态下的电阻的比率恒定或基本恒定，而与环境温度无关。可以通过增加，减少或保持相同的复位电流和/或设定电流来维持该比率。

83. 发明授权

US08243508B2 Resistive memory devices using assymetrical bitline charging and discharging 有权
标题翻译：使用不对称位线充电和放电的电阻式存储器件
公开(公告)号：US08243508B2
公开(公告)日：2012-08-14
申请号：US13216832
申请日：2011-08-24
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00 , G11C8/08
CPC分类号： G11C7/18 , G11C7/12 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/004 , G11C13/0069
摘要： A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.
摘要翻译：非易失性存储器件包括多个存储体，每个存储体包括多个非易失性电阻存储单元（例如PRAM单元）。该设备还包括由存储体共享的写入全局位线和由存储体共享的读出的全局位线。该装置还包括控制电路，其被配置为使用读写全局位线在第一存储体中使用读出的全局位线从第一存储体中的选定的非易失性存储单元读取数据，从而将数据写入到第一存储体中的选定的非易失性存储单元，写入全局位线的时间段比流经第一存储体的非易失性存储单元的写入电流的淬灭时间长。

84. 发明授权

US08228720B2 Nonvolatile memory devices including variable resistive elements 有权
标题翻译：包括可变电阻元件的非易失性存储器件
公开(公告)号：US08228720B2
公开(公告)日：2012-07-24
申请号：US12556787
申请日：2009-09-10
申请人： Byung-Gil Choi , Hye-Jin Kim
发明人： Byung-Gil Choi , Hye-Jin Kim
IPC分类号： G11C7/04 , G11C8/08 , G11C11/21 , G11C8/10
CPC分类号： G11C8/08 , G11C13/0004 , G11C13/0028 , G11C2213/72
摘要： A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.
摘要翻译：非易失性存储器件可以包括存储单元阵列，该存储单元阵列具有以矩阵形式布置的多个非易失性存储单元，包括多行非易失性存储单元。多个字线中的每一个可以与矩阵的相应行的非易失性存储器单元耦合。行解码器可以耦合到多个字线，其中行解码器被配置为使用具有响应于温度变化调节的电平的行偏置来禁用至少一个字线。这种非易失性存储器件可以以减少的待机电流工作。

85. 发明授权

US08199603B2 Nonvolatile memory devices having variable-resistance memory cells and methods of programming the same 有权
标题翻译：具有可变电阻存储单元的非易失性存储器件及其编程方法
公开(公告)号：US08199603B2
公开(公告)日：2012-06-12
申请号：US12498549
申请日：2009-07-07
申请人： Won-Ryul Chung , Byung-Gil Choi , In-Cheol Shin , Ki-Won Lim
发明人： Won-Ryul Chung , Byung-Gil Choi , In-Cheol Shin , Ki-Won Lim
IPC分类号： G11C8/00
CPC分类号： G11C13/0038 , G11C8/10 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/72 , G11C2213/79
摘要： Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.
摘要翻译：非易失性存储器件包括可变电阻存储器单元阵列和电耦合到阵列的写入驱动器。写入驱动器被配置为在用于编程所述阵列中的可变电阻存储器单元的操作期间，在具有至少两个不相等的位线电压的阶梯序列的驱动可变电阻存储器单元阵列中的位线。至少两个不等位线电压的阶梯级序列包括第一步骤的预充电电压（例如Vcc-Vth）和跟随第一步骤的第二步骤的较高升压电压（例如，Vpp-Vth）。

86. 发明申请

US20110317484A1 RESISTIVE MEMORY DEVICES USING ASSYMETRICAL BITLINE CHARGING AND DISCHARGING 有权
标题翻译：使用组合式电子充电和放电的电阻式存储器件
公开(公告)号：US20110317484A1
公开(公告)日：2011-12-29
申请号：US13216832
申请日：2011-08-24
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C7/18 , G11C7/12 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/004 , G11C13/0069
摘要： A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.
摘要翻译：非易失性存储器件包括多个存储体，每个存储体包括多个非易失性电阻存储单元（例如PRAM单元）。该设备还包括由存储体共享的写入全局位线和由存储体共享的读出的全局位线。该装置还包括控制电路，其被配置为使用读写全局位线在第一存储体中使用读出的全局位线从第一存储体中的选定的非易失性存储单元读取数据，从而将数据写入到第一存储体中的选定的非易失性存储单元，写入全局位线的时间段比流经第一存储体的非易失性存储单元的写入电流的淬灭时间长。

87. 发明授权

US08077496B2 Nonvolatile memory device and method of driving the same 失效
标题翻译：非易失存储器件及其驱动方法
公开(公告)号：US08077496B2
公开(公告)日：2011-12-13
申请号：US12585730
申请日：2009-09-23
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C2013/009
摘要： A nonvolatile memory and a method of driving the same are provided, which adopt an improved write verify operation. The method of driving a nonvolatile memory device having variable resistance memory cells, bit lines coupled to the variable resistance memory cells, and column selection transistors coupled between the variable resistance memory cells and the bit lines to receive a first control voltage being applied to their gates, includes making the first control voltage at a first level, and changing a resistance of the variable resistance memory cells by providing a write bias to the variable resistance cells; verifying and reading whether the changed resistance enters into a specified resistance window; and changing the first control voltage to a second level that is different from the first level, and changing the resistance of the variable resistance memory cells by providing the write bias to the variable resistance memory cells.
摘要翻译：提供了一种非易失性存储器及其驱动方法，其采用改进的写校验操作。驱动具有可变电阻存储单元的非易失性存储器件的方法，耦合到可变电阻存储单元的位线和耦合在可变电阻存储单元与位线之间的列选择晶体管，以接收施加到其栅极的第一控制电压包括使第一控制电压处于第一电平，并通过向可变电阻单元提供写入偏置来改变可变电阻存储单元的电阻; 验证和读取改变的电阻是否进入指定的电阻窗口; 以及将所述第一控制电压改变到与所述第一电平不同的第二电平，以及通过向所述可变电阻存储单元提供所述写入偏置来改变所述可变电阻存储单元的电阻。

88. 发明授权

US07852666B2 Nonvolatile memory using resistance material 有权
标题翻译：使用电阻材料的非易失性存储器
公开(公告)号：US07852666B2
公开(公告)日：2010-12-14
申请号：US12243578
申请日：2008-10-01
申请人： Joon-Yong Choi , Byung-Gil Choi
发明人： Joon-Yong Choi , Byung-Gil Choi
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C13/0069 , G11C7/18 , G11C8/14 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2013/0078
摘要： A nonvolatile memory using a resistance material includes first and second memory-cell blocks having different block address information and each including a plurality of nonvolatile memory cells; a global bitline common to the first and second memory-cell blocks; first and second local bitlines corresponding to the first and second memory-cell blocks, respectively, and coupled to each other; and a common bitline selection circuit interposed between the first and second memory-cell blocks and coupled between the first and second local bitlines and the global bitline.
摘要翻译：使用电阻材料的非易失性存储器包括具有不同块地址信息并且各自包括多个非易失性存储单元的第一和第二存储单元块; 第一和第二存储单元块共同的全局位线; 分别对应于第一和第二存储单元块的第一和第二局部位线并彼此耦合; 以及插入在第一和第二存储单元块之间并耦合在第一和第二本地位线与全局位线之间的公共位线选择电路。

89. 发明授权

US07817479B2 Nonvolatile memory device using a variable resistive element and associated operating method 有权
标题翻译：使用可变电阻元件和相关操作方法的非易失性存储器件
公开(公告)号：US07817479B2
公开(公告)日：2010-10-19
申请号：US12136822
申请日：2008-06-11
申请人： Yu-Hwan Ro , Byung-Gil Choi , In-Cheol Shin
发明人： Yu-Hwan Ro , Byung-Gil Choi , In-Cheol Shin
IPC分类号： G11C16/04
CPC分类号： G11C13/00 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.
摘要翻译：使用提供在存储器件外部的电压和在器件内产生的电压而不是仅使用在器件内产生的电压作为驱动电压的非易失性存储器件避免了当出现瞬时显着电压下降时存储器件的故障。非易失性存储器件包括多个非易失性存储器单元，耦合到多个非易失性存储器单元的至少一部分的位线，耦合到位线的列选择晶体管和驱动电路。驱动电路耦合到列选择晶体管的栅极，并且被配置为使用其中第二电压高于第一电压的第一电压和第二电压向栅极提供电荷。

90. 发明申请

US20100142249A1 NONVOLATILE MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20100142249A1
公开(公告)日：2010-06-10
申请号：US12630317
申请日：2009-12-03
申请人： Byung-Gil Choi
发明人： Byung-Gil Choi
IPC分类号： G11C5/06 , G11C11/00
CPC分类号： G11C7/18 , G11C13/0004
摘要： A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile memory cells, write global bit lines shared by the plurality of memory banks, read global bit lines shared by the plurality of memory banks, and a dummy global bit line arranged between the write global bit lines and the read global bit lines, wherein the dummy global bit line is configured and operable to reduce noise affecting a write bit line involved in a write operation or noise affecting a read global bit line involved in a read operation.
摘要翻译：非易失性存储器件包括多个存储体，每个存储体包括多个非易失性存储器单元，由多个存储体组共享的写入全局位线，由多个存储体组共享的读出全局位线以及虚拟全局位线布置在写入全局位线和读取全局位线之间，其中虚拟全局位线被配置和可操作以减少影响写入操作中涉及的写入位线的噪声或影响读取操作中涉及的读取全局位线的噪声。

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