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81. 发明申请

US20120137515A1 THROUGH WAFER VIAS WITH DISHING CORRECTION METHODS 有权
标题翻译：通过具有循环校正方法的WAVER VIAS
公开(公告)号：US20120137515A1
公开(公告)日：2012-06-07
申请号：US13369414
申请日：2012-02-09
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.
摘要翻译：提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。

82. 发明申请

US20120122293A1 METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL 有权
标题翻译：在FEOL中形成MIM电容结构的方法
公开(公告)号：US20120122293A1
公开(公告)日：2012-05-17
申请号：US13359032
申请日：2012-01-26
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译：电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器由第二电容器板，电容器电介质层和半导体衬底形成。

83. 发明授权

US08166651B2 Through wafer vias with dishing correction methods 有权
标题翻译：通过具有凹陷校正方法的晶片通孔
公开(公告)号：US08166651B2
公开(公告)日：2012-05-01
申请号：US12181359
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01K3/10 , H05K3/02 , H05K3/10 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a through wafer via including forming the through wafer via (TWV) into a substrate and through a first dielectric layer over the substrate; planarizing the first dielectric layer using a chemical mechanical polish before forming a second dielectric layer; forming the second dielectric layer over the substrate and the TWV; forming at least one first contact through the second dielectric layer and to the TWV; forming at least one second contact through the second dielectric layer and the first dielectric layer directly and electrically connected to another structure upon the substrate; and forming a first metal wiring layer directly over the second dielectric layer, the first metal wiring layer directly and physically contacting the at least one first contact and the at least one second contact.
摘要翻译：一种形成贯穿晶片通孔的方法，包括通过（TWV）形成贯穿晶片进入衬底并穿过衬底上的第一介电层; 在形成第二电介质层之前，使用化学机械抛光平面化第一介电层; 在所述衬底和所述TWV上形成所述第二电介质层; 通过所述第二介电层和所述TWV形成至少一个第一接触; 通过所述第二电介质层和所述第一介电层形成至少一个第二接触，并且在所述衬底上直接电连接到另一结构; 以及直接在所述第二电介质层上方形成第一金属布线层，所述第一金属布线层直接地和物理地接触所述至少一个第一触点和所述至少一个第二触点。

84. 发明授权

US08138008B1 Forming an oxide MEMS beam 有权
标题翻译：形成氧化物MEMS光束
公开(公告)号：US08138008B1
公开(公告)日：2012-03-20
申请号：US12955224
申请日：2010-11-29
申请人： Joseph P. Hasselbach , Karen L. Lestage , Anthony K. Stamper
发明人： Joseph P. Hasselbach , Karen L. Lestage , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B81C1/00666 , B81B2203/0118 , B81C1/00111
摘要： Solutions for forming a semiconductor including an oxide MEMS beam are disclosed. In one embodiment, a method of forming a beam within a sealed cavity includes: depositing a lower insulator layer comprising one or more layers; depositing an upper insulator layer over the first insulator layer, the upper insulator layer comprising one or more layers, wherein a composite stress of the upper insulator layer is different than a composite stress of the lower insulator layer.
摘要翻译：公开了用于形成包括氧化物MEMS光束的半导体的解决方案。在一个实施例中，在密封空腔内形成梁的方法包括：沉积包括一层或多层的下绝缘体层; 在所述第一绝缘体层上沉积上绝缘体层，所述上绝缘体层包括一层或多层，其中所述上绝缘体层的复合应力不同于所述下绝缘体层的复合应力。

85. 发明授权

US08136084B2 Arranging through silicon vias in IC layout 有权
标题翻译：在IC布局中排列硅通孔
公开(公告)号：US08136084B2
公开(公告)日：2012-03-13
申请号：US12555981
申请日：2009-09-09
申请人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
发明人： Donald R. Dean, Jr. , Peter J. Lindgren , Glen L. Miles , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G06F17/52
CPC分类号： H01L21/76898 , G06F17/5072
摘要： A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.
摘要翻译：评估包括多个贯穿硅通孔（TSV）的IC布局的一部分以识别线性对准的TSV。修改IC布局的部分以减少多个线性对齐的TSV，导致较少的晶片断裂。

86. 发明授权

US08129286B2 Reducing effective dielectric constant in semiconductor devices 有权
标题翻译：降低半导体器件中的有效介电常数
公开(公告)号：US08129286B2
公开(公告)日：2012-03-06
申请号：US12139803
申请日：2008-06-16
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
摘要翻译：制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成亚光刻特征跨越至少一个互连的侧壁。

87. 发明授权

US08119491B2 Methods of fabricating passive element without planarizing and related semiconductor device 有权
标题翻译：无平面化制造无源元件及相关半导体器件的方法
公开(公告)号：US08119491B2
公开(公告)日：2012-02-21
申请号：US12106374
申请日：2008-04-21
申请人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L21/20
CPC分类号： H01L21/76819 , H01L23/522 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.
摘要翻译：公开了制造无源元件的方法和包括无源元件的半导体器件，其包括使用虚拟无源元件。虚拟无源元件是被添加到芯片布局以帮助平坦化但在有源电路中不使用的无源元件或线。该方法的一个实施例包括形成无源元件和邻近无源元件的虚拟无源元件; 在无源元件和虚拟无源元件上形成电介质层，其中介电层在无源元件和虚拟无源元件之间基本上是平面的; 并且在电介质层中形成通过电介质层与无源元件的互连以及与虚拟无源元件的至少一部分重叠的虚拟互连部分。该方法消除了平面化的需要。

88. 发明申请

US20110315528A1 PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
标题翻译：平面CAVITY MEMS及相关结构，制造方法和设计结构
公开(公告)号：US20110315528A1
公开(公告)日：2011-12-29
申请号：US12977850
申请日：2010-12-23
申请人： Russell T. HERRIN , Jeffrey C. Maling , Anthony K. Stamper
发明人： Russell T. HERRIN , Jeffrey C. Maling , Anthony K. Stamper
IPC分类号： H01H57/00 , G06F17/50 , H01L21/56
CPC分类号： B81B3/0072 , B81B3/0021 , B81B2201/01 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81C1/0015 , B81C1/00365 , B81C1/00476 , B81C1/00619 , B81C1/00626 , B81C1/00666 , B81C2201/0109 , B81C2201/013 , B81C2201/0167 , B81C2201/017 , B81C2203/0136 , B81C2203/0172 , G06F17/5068 , G06F17/5072 , H01H1/0036 , H01H57/00 , H01H59/0009 , H01H2057/006 , H01L41/1136 , H01L2924/0002 , Y10S438/937 , Y10T29/42 , Y10T29/435 , Y10T29/49002 , Y10T29/49105 , Y10T29/49121 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/5313 , H01L2924/00
摘要： A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.
摘要翻译：形成至少一个微电子机械系统（MEMS）的方法包括在远离梁结构的绝缘体层上形成梁结构和电极。该方法还包括在光束结构上方并且远离电极形成至少一个牺牲层。该方法还包括在至少一个牺牲层和电极上形成盖结构。该方法还包括同时提供穿过盖结构的通气孔以暴露牺牲层并在电极上形成部分通孔。该方法还包括排出牺牲层以形成空腔。该方法还包括用材料密封通气孔。该方法还包括通过部分通孔在盖结构中形成最终通孔至电极。

89. 发明授权

US08013367B2 Structure and method for compact long-channel FETs 失效
标题翻译：紧凑型长沟道FET的结构和方法
公开(公告)号：US08013367B2
公开(公告)日：2011-09-06
申请号：US11937161
申请日：2007-11-08
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1037 , H01L29/6659 , H01L29/66621
摘要： A compact semiconductor structure including at least one FET located upon and within a surface of a semiconductor substrate in which the at least one FET includes a long channel length and/or a wide channel width and a method of fabricating the same are provided. In some embodiments, the ordered, nanosized pattern is oriented in a direction that is perpendicular to the current flow. In such an embodiment, the FET has a long channel length. In other embodiments, the ordered, nanosized pattern is oriented in a direction that is parallel to that of the current flow. In such an embodiment, the FET has a wide channel width. In yet another embodiment, one ordered, nanosized pattern is oriented in a direction perpendicular to the current flow, while another ordered, nanosized pattern is oriented in a direction parallel to the current flow. In such an embodiment, a FET having a long channel length and wide channel width is provided.
摘要翻译：一种紧凑的半导体结构，其包括至少一个位于半导体衬底的表面之上和之中的FET，其中所述至少一个FET包括长沟道长度和/或宽沟道宽度及其制造方法。在一些实施例中，有序的纳米尺寸图案在垂直于电流的方向上取向。在这样的实施例中，FET具有长的沟道长度。在其他实施例中，有序的纳米尺寸图案在平行于电流流动的方向上取向。在这样的实施例中，FET具有宽的通道宽度。在另一个实施例中，一个有序的纳米尺寸图案在垂直于电流的方向上定向，而另一个有序的纳米尺寸图案在平行于电流的方向上取向。在这样的实施例中，提供具有长沟道长度和宽沟道宽度的FET。

90. 发明申请

US20110177435A1 Photomasks having sub-lithographic features to prevent undesired wafer patterning 审中-公开
标题翻译：具有亚光刻特征以防止不期望的晶片图案化的光掩模
公开(公告)号：US20110177435A1
公开(公告)日：2011-07-21
申请号：US12690312
申请日：2010-01-20
申请人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
发明人： Russell T. Herrin , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： G03F1/00
CPC分类号： G03F1/42 , G03F1/36 , G03F1/38
摘要： A photomask that is used as a light filter in an exposure system is made of at least one layer of material comprising one or more transparent regions and one or more non-transparent regions. The difference between the transparent regions and the non-transparent regions defines the features that will be illuminated by the exposure system on a photoresist that will be exposed using the exposure system. The features comprise one or more device shapes and at least one sub-lithographic shape that will be exposed upon the photoresist. The sub-lithographic shape has an sub-lithographic shape size that is limited in such a way that the sub-lithographic shape causes a physical change only in a surface of the photoresist. Therefore, because the sub-lithographic shape is so small, it avoids forming an opening through the photoresist after the photoresist is developed and only causes a change on the surface of the photoresist.
摘要翻译：在曝光系统中用作滤光器的光掩模由包括一个或多个透明区域和一个或多个不透明区域的至少一层材料制成。透明区域和不透明区域之间的差异限定了曝光系统将在将使用曝光系统曝光的光刻胶上照亮的特征。这些特征包括一个或多个器件形状和将被暴露在光刻胶上的至少一个亚光刻形状。亚光刻形状具有亚光刻形状尺寸，其受到限制，使得亚光刻形状仅在光致抗蚀剂的表面引起物理变化。因此，由于亚光刻形状如此之小，因此避免了在光致抗蚀剂显影之后通过光致抗蚀剂形成开口，并且仅引起光致抗蚀剂表面的变化。

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