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81. 发明授权

US08281083B2 Device, system and method of generating an execution instruction based on a memory-access instruction 有权
标题翻译：基于存储器访问指令生成执行指令的装置，系统和方法
公开(公告)号：US08281083B2
公开(公告)日：2012-10-02
申请号：US11170115
申请日：2005-06-30
申请人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
发明人： Alon Naveh , Eliezer Weissmann , Itamar Kazachinsky , Iris Sorani , Yair Kazarinov
IPC分类号： G06F13/12
CPC分类号： G06F1/3203 , G06F1/3234 , G06F1/325 , G06F9/30083
摘要： Embodiments of the present invention provide an apparatus, system, and method of generating an execution instruction. Some demonstrative embodiments my include generating an execution instruction of a predetermined executable format based on memory address data of a memory-access instruction representing a memory address. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供了一种生成执行指令的装置，系统和方法。一些说明性实施例，我的包括基于表示存储器地址的存储器访问指令的存储器地址数据生成预定可执行格式的执行指令。描述和要求保护其他实施例。

82. 发明申请

US20120185709A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING THREAD CONSOLIDATION 有权
标题翻译：能源效率和能源保护的方法，装置和系统，包括螺纹综合
公开(公告)号：US20120185709A1
公开(公告)日：2012-07-19
申请号：US13327692
申请日：2011-12-15
申请人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman
发明人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/3234 , Y02D10/152 , Y02D50/20
摘要： An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.
摘要翻译：这里描述了用于线程合并的装置，方法和系统。当前的处理器利用率得到确定。并且从处理器利用率和其他执行参数来识别合并机会，例如在合并之后估计新的利用率，确定基于新利用率是否能够节省能源，以及执行线程迁移/合并到活动处理元件的子集。一旦执行整合，现在处于空闲状态的非子集处理元件被关闭以节省能量并提供节能的执行环境。

83. 发明授权

US10558490B2 Mechanism for issuing requests to an accelerator from multiple threads 有权
公开(公告)号：US10558490B2
公开(公告)日：2020-02-11
申请号：US13992865
申请日：2012-03-30
申请人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann
发明人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann
IPC分类号： G06F9/48 , G06F12/1027
摘要： An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.

84. 发明申请

US20160246597A1 APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
标题翻译：低速延迟加速器的装置和方法
公开(公告)号：US20160246597A1
公开(公告)日：2016-08-25
申请号：US15145748
申请日：2016-05-03
申请人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
发明人： Oren Ben-Kiki , llan Pardo , Robert Valentine , Eliezer Weissmann , Dror Markovich , Yuval Yosef
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30043 , G06F9/30076 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/384 , G06F9/3877 , G06F9/3879 , G06F9/3881 , G06F9/54 , G06F11/0721 , G06F11/0724 , G06F11/0772 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.
摘要翻译：描述了一种用于提供加速器的低延迟调用的装置和方法。例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据并响应于尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功地执行命令，则一个或多个加速器将存储包括结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

85. 发明授权

US09164923B2 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform 有权
标题翻译：动态固定异构计算平台的不同类型处理器之间共享的虚拟页面
公开(公告)号：US09164923B2
公开(公告)日：2015-10-20
申请号：US13175489
申请日：2011-07-01
申请人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
发明人： Gad Sheaffer , Boris Ginzburg , Ronny Ronen , Eliezer Weissmann
IPC分类号： G06F12/08 , G06F12/10 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/0804 , G06F12/126 , G06F13/1663 , G06F2212/303 , G06F2212/657 , G06F2212/684
摘要： A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device (e.g., a graphics processing unit, GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. In one embodiment, the device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.
摘要翻译：计算机系统可以支持一种或多种技术来允许由非CPU设备（例如，图形处理单元，GPU）访问的存储器页的动态固定。非CPU可以支持虚拟到物理地址映射，并且因此可以知道可能不被固定但可被非CPU访问的存储器页。非CPU可以向诸如与CPU相关联的设备驱动程序的运行时组件通知或发送这样的信息。在一个实施例中，设备驱动程序可以动态地执行可由非CPU访问的这种存储器页的钉扎。设备驱动程序甚至可以取消内存页，这可能不再被非CPU访问。这样的方法可以允许非CPU可以不再访问的存储器页面可用于分配给其他CPU和/或非CPU。

86. 发明授权

US09098261B2 User level control of power management policies 有权
标题翻译：电源管理政策的用户级别控制
公开(公告)号：US09098261B2
公开(公告)日：2015-08-04
申请号：US13326586
申请日：2011-12-15
申请人： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
发明人： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/266 , G06F1/3203 , G06F1/3206 , G06F1/3234
摘要： In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有核心的处理器和用于控制处理器的电源管理特征的功率控制器。功率控制器可以从核心接收能量性能偏差（EPB）值，并根据该值访问功率性能调谐表。使用表中的信息，可以更新电源管理功能的至少一个设置。描述和要求保护其他实施例。

87. 发明授权

US09075610B2 Method, apparatus, and system for energy efficiency and energy conservation including thread consolidation 有权
标题翻译：节能，节能，包括螺纹固结的方法，装置和系统
公开(公告)号：US09075610B2
公开(公告)日：2015-07-07
申请号：US13327692
申请日：2011-12-15
申请人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman
发明人： Eliezer Weissmann , Efraim Rotem , Avinash N. Ananthakrishnan , Alon Naveh , Hisham Abu Salah , Nadav Shulman
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3243 , G06F1/3234 , Y02D10/152 , Y02D50/20
摘要： An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.
摘要翻译：这里描述了用于线程合并的装置，方法和系统。当前的处理器利用率得到确定。并且从处理器利用率和其他执行参数来识别合并机会，例如在合并之后估计新的利用率，确定基于新利用率是否能够节省能源，以及执行线程迁移/合并到活动处理元件的子集。一旦执行整合，现在处于空闲状态的非子集处理元件被关闭以节省能量并提供节能的执行环境。

88. 发明授权

US09058201B2 Managing and tracking thread access to operating system extended features using map-tables containing location references and thread identifiers 有权
标题翻译：使用包含位置引用和线程标识符的映射表来管理和跟踪对操作系统扩展功能的线程访问
公开(公告)号：US09058201B2
公开(公告)日：2015-06-16
申请号：US13993471
申请日：2011-12-28
申请人： Michael Mishaeli , James B. Crossland , Boris Ginzburg , Eliezer Weissmann
发明人： Michael Mishaeli , James B. Crossland , Boris Ginzburg , Eliezer Weissmann
IPC分类号： G06F9/46 , G06F9/44 , G06F9/48 , G06F9/445
CPC分类号： G06F9/461 , G06F9/44 , G06F9/445 , G06F9/46 , G06F9/48
摘要： Extended features such as registers and functions within processors are made available to operating systems (OS) using an extended-state driver and by modifying instruction set extensions, such as XSAVE. A map-table designates a correspondence between memory locations for storing data relating to extended features not supported by the OS and called by an application. As a result, applications may utilize processor resources which are unsupported by the OS.
摘要翻译：扩展功能（如处理器内的寄存器和功能）可以使用扩展状态驱动程序和修改指令集扩展（如XSAVE）对操作系统（OS）可用。映射表指定用于存储与OS不支持并被应用程序调用的扩展特征有关的数据的存储器位置之间的对应关系。因此，应用程序可能利用OS不支持的处理器资源。

89. 发明授权

US09053022B2 Synchronous software interface for an accelerated compute engine 有权
标题翻译：用于加速计算引擎的同步软件界面
公开(公告)号：US09053022B2
公开(公告)日：2015-06-09
申请号：US13994371
申请日：2011-12-30
申请人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann
发明人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann
IPC分类号： G06F11/00 , G06F11/07 , G06F9/54 , G06F11/14 , G06F9/44 , G06F9/38
CPC分类号： G06F11/0724 , G06F9/3881 , G06F9/4484 , G06F9/54 , G06F9/542 , G06F11/0793 , G06F11/1474
摘要： Some implementations disclosed herein provide techniques and arrangements for a synchronous software interface for a specialized logic engine. The synchronous software interface may receive, from a first core of a plurality of cores, a control block including a transaction for execution by the specialized logic engine. The synchronous software interface may send the control block to the specialized logic engine and wait to receive a confirmation from the specialized logic engine that the transaction was successfully executed.
摘要翻译：本文中公开的一些实施例提供了用于专用逻辑引擎的同步软件接口的技术和布置。同步软件接口可以从多个核心的第一核心接收包括专用逻辑引擎执行的事务的控制块。同步软件接口可以将控制块发送到专用逻辑引擎，并等待从专门的逻辑引擎接收事务成功执行的确认。

90. 发明授权

US08799687B2 Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates 有权
标题翻译：能量效率和节能的方法，装置和系统，包括在变化的唤醒速率下优化C状态选择
公开(公告)号：US08799687B2
公开(公告)日：2014-08-05
申请号：US13339284
申请日：2011-12-28
申请人： Alon Naveh , Eliezer Weissmann , Ofer Nathan , Nadav Shulman
发明人： Alon Naveh , Eliezer Weissmann , Ofer Nathan , Nadav Shulman
IPC分类号： G06F1/00 , G06F1/32 , G06F13/24 , G06F15/00
CPC分类号： G06F1/3275 , G06F1/3203 , G06F1/3206 , G06F1/3243 , G06F1/3246 , G06F1/3296 , Y02D10/152 , Y02D10/172
摘要： A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.
摘要翻译：处理器可以包括动态地为处理核心选择最佳C状态的电源管理技术。对操作系统的实际工作负载的测量表现出两个重要的观察结果：（1）高中断率的突发散布在低中断速率周期和长时间的高活动水平之间; 和（2）中断率可能突然降低到当前操作系统（OS）的典型值的中断速率（例如，1毫秒）。功率控制逻辑可以基于存储在计数器中的陈旧数据来确定C状态，而不是通过覆盖由OS或任何其它功率监视逻辑确定的C状态来确定最佳C状态。功率控制逻辑可以动态地基于CPU空闲驻留时间和可变速率唤醒事件来确定最佳C状态以匹配预期的唤醒事件速率。

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