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    • 83. 发明申请
    • Method and system for expanding flash storage device capacity
    • 扩展闪存设备容量的方法和系统
    • US20050286284A1
    • 2005-12-29
    • US10882005
    • 2004-06-29
    • Sun-Teck SeeHorng-Yee ChouCharles Lee
    • Sun-Teck SeeHorng-Yee ChouCharles Lee
    • G11C5/00G11C11/34G11C16/02
    • G11C16/02
    • Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.
    • 通过使用具有闪存控制器的分配逻辑单元,单个主芯片使能被解复用到多个次级芯片中,使得能够用于多个闪存芯片或芯片。 这样做,Flash存储设备容量大大扩大。 在第一方面,一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面,印刷电路板(PCB)包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号,并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。
    • 84. 发明申请
    • Method and system for expanding flash storage device capacity
    • 扩展闪存设备容量的方法和系统
    • US20050285248A1
    • 2005-12-29
    • US10881203
    • 2004-06-29
    • Sun-Teck SeeHorng-Yee ChouCharles Lee
    • Sun-Teck SeeHorng-Yee ChouCharles Lee
    • G11C5/04H01L23/02H01L23/495H01L23/50H01L25/10H05K1/18
    • G11C5/04H01L23/49575H01L23/50H01L24/48H01L25/105H01L2224/32145H01L2224/48091H01L2224/48247H01L2225/1029H01L2225/1058H01L2924/00014H01L2924/181H05K1/181H05K2201/10515H05K2201/10689Y02P70/611H01L2924/00012H01L2224/45099H01L2224/45015H01L2924/207
    • A memory package and a chip architecture which includes stacked multiple memory chips is described. In a first aspect, a memory package comprises a substrate and a plurality of memory dies mounted on the substrate. Each die has a separate chip enable. In a second aspect, a chip architecture comprises a printed circuit board (PCB). The PCB includes a footprint. The footprint includes at least one no connect (NC) pad. The chip architecture includes a plurality of stacked memory chips mounted on the printed circuit board. Each of the plurality of stacked memory has a chip enable signal pin and also has at least one NC pin. At least one of the plurality of stacked memory chips utilizes an NC pin of another of the stacked memory chips to route the chip enable pin to at least one NC pad of the footprint. Accordingly, a system and method in accordance with the present invention provides for increased memory density within a particular space constraint by (1) providing multiple dies in a single memory package and (2) by providing stacked memory chips in a single PCB footprint. In so doing, the package/PCB will have increased memory density over a conventional package/PCB within the same space constraints, and the capacity of Flash storage devices is expanded accordingly.
    • 描述了包括堆叠的多个存储器芯片的存储器封装和芯片架构。 在第一方面,一种存储器封装包括衬底和安装在衬底上的多个存储器管芯。 每个管芯都有独立的芯片使能。 在第二方面,芯片架构包括印刷电路板(PCB)。 PCB包括一个占位面积。 足迹包括至少一个无连接(NC)垫。 芯片架构包括安装在印刷电路板上的多个堆叠的存储器芯片。 多个堆叠存储器中的每一个具有芯片使能信号引脚,并且还具有至少一个NC引脚。 多个层叠的存储器芯片中的至少一个利用另一个堆叠的存储器芯片的NC引脚将芯片使能引脚路由到占用空间的至少一个NC焊盘。 因此,根据本发明的系统和方法通过(1)在单个存储器封装中提供多个管芯并且(2)通过在单个PCB封装中提供堆叠的存储器芯片来提供特定空间约束内的增加的存储器密度。 在这样做的同时,封装/ PCB将在相同的空间限制内在传统封装/ PCB上增加存储密度,并相应地扩展闪存存储设备的容量。
    • 85. 发明申请
    • Highly integrated mass storage device with an intelligent flash controller
    • 高度集成的大容量存储设备,带有智能闪存控制器
    • US20050160218A1
    • 2005-07-21
    • US10761853
    • 2004-01-20
    • Sun-Teck SeeTzu-Yih ChuBen-Wei ChenHorng-yee ChouSzu-Kuang ChouCharles Lee
    • Sun-Teck SeeTzu-Yih ChuBen-Wei ChenHorng-yee ChouSzu-Kuang ChouCharles Lee
    • G06F3/06G06F12/00G06F13/16G06F13/40
    • G06F13/405G06F3/0601G06F13/1694G06F2003/0694
    • A FLASH controller is disclosed. The controller comprises a USB interface unit. The USB interface unit implements a USB standard that has a bus speed equal or greater than 12 Mb/s. The controller includes an internal bus coupled to the USB interface unit; and a FLASH interface unit coupled to the internal bus. The FLASH interface unit includes FLASH controller logic that allows the throughput for access to the FLASH memory to match the speed of the USB standard. Advantages of the FLASH controller in accordance with the present invention include (1) utilizing the higher speed USB interface such as the USB 2.0 standard, which substantially increases the serial throughput between USB host and FLASH controller; (2) utilizing more advanced FLASH control logic which is implemented to raise the throughput for the FLASH memory access; (3) utilizing an intelligent algorithm to detect and access the different FLASH types, which broadens the sourcing and the supply of FLASH memory; (4) by storing the software program along with data in FLASH memory which results in the cost of the controller being reduced, and also makes the software program field changeable and upgradeable; and (5) providing high integration, which substantially reduces the overall space needed and reduces the complexity and the cost of manufacturing.
    • 公开了一种闪存控制器。 控制器包括USB接口单元。 USB接口单元实现总线速度等于或大于12 Mb / s的USB标准。 该控制器包括耦合到USB接口单元的内部总线; 以及耦合到内部总线的FLASH接口单元。 FLASH接口单元包括FLASH控制器逻辑,允许访问闪速存储器的吞吐量与USB标准的速度相匹配。 根据本发明的闪存控制器的优点包括(1)利用诸如USB 2.0标准的更高速USB接口,其大大增加了USB主机和闪存控制器之间的串行吞吐量; (2)利用更高级的FLASH控制逻辑,其实现以提高FLASH存储器访问的吞吐量; (3)利用智能算法检测和访问不同的FLASH类型,拓宽了FLASH存储器的采购和供应; (4)通过将软件程序与FLASH存储器中的数据一起存储,从而降低控制器的成本,并使软件程序区域可以更改和升级; 和(5)提供高集成度,这大大降低了所需的总体空间并降低了制造的复杂性和成本。
    • 89. 发明申请
    • Conduit Hanger And Support Apparatus
    • 管道衣架和支撑装置
    • US20140175230A1
    • 2014-06-26
    • US13748656
    • 2013-01-24
    • Charles LeeElio EvangelistaPaul Burke
    • Charles LeeElio EvangelistaPaul Burke
    • F16L3/26
    • F16L3/26F16L3/11H02G3/263Y10T29/49
    • A support assembly for supporting a conduit includes a support, a clamp, and a hanger. The support has a partial-cylindrical shape including a first section having a first diameter and a second section having a second diameter that is greater than the first diameter. In one aspect, at least one of the first section and the second section define a first aperture in the partial-cylindrical shape. In another aspect, at least one of the first section and the second section includes a retention member extending radially from an outer surface of the partial-cylindrical shape. The retention member includes a closed loop or a partially-open loop that defines a second aperture for receiving a strap to secure the conduit to the support. The clamp is configured to secure the conduit to the support. The hanger is configured to suspend the support from a structure.
    • 用于支撑导管的支撑组件包括支撑件,夹具和悬挂器。 支撑件具有部分圆柱形形状,其包括具有第一直径的第一部分和具有大于第一直径的第二直径的第二部分。 在一个方面,第一部分和第二部分中的至少一个限定了部分圆柱形形状的第一孔。 在另一方面,第一部分和第二部分中的至少一个包括从部分圆柱形形状的外表面径向延伸的保持部件。 保持构件包括闭环或部分开放的环,其限定用于接收带以将导管固定到支撑件的第二孔。 夹具被配置成将导管固定到支撑件上。 吊架构造成将结构悬挂在支架上。