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81. 发明授权

US09921997B2 Mechanism for PCIE cable topology discovery in a rack scale architecture environment 有权
公开(公告)号：US09921997B2
公开(公告)日：2018-03-20
申请号：US15089403
申请日：2016-04-01
申请人： Intel Corporation
发明人： Mohan J. Kumar , Murugasamy K. Nachimuthu
IPC分类号： G06F13/42 , G06F12/02 , G06F13/40 , G06F3/06 , G06F11/30 , G06F11/22
CPC分类号： G06F13/4282 , G06F3/0664 , G06F3/0688 , G06F11/221 , G06F11/2221 , G06F11/3027 , G06F12/0246 , G06F13/4022 , G06F2212/7201
摘要： A mechanism for PCIe cable topology discovery in a Rack Scale Architecture (RSA) and associated methods, apparatus, and systems. Pooled system drawers installed in rack are interconnected via multiple PCIe cables coupled to PCIe ports on the pooled system drawers. The PCIe ports are associated with host ports connections between server nodes and host ports in respective pooled system drawers are automatically detected, with corresponding PCIe connection information being automatically generated and aggregated to determine the PCIe cable topology for the rack. In one aspect, PCIe devices are emulated for each host port in a pooled storage drawer including pooled PCIe storage devices. Server nodes in a pooled compute drawer send PCIe configuration messages over the PCIe cables, with returned reply messages generated by the emulated PCIe devices identifying the host ports. Information pertaining to the host ports, pooled system drawers, and server nodes is used to determine the PCIe cable topology.

82. 发明申请

US20160378344A1 PROCESSOR AND PLATFORM ASSISTED NVDIMM SOLUTION USING STANDARD DRAM AND CONSOLIDATED STORAGE 审中-公开
标题翻译：使用标准DRAM和综合存储的处理器和平台辅助NVDIMM解决方案
公开(公告)号：US20160378344A1
公开(公告)日：2016-12-29
申请号：US14748798
申请日：2015-06-24
申请人： INTEL CORPORATION
发明人： Murugasamy K. Nachimuthu , Mohan J. Kumar , George Vergis
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/065 , G06F3/061 , G06F3/0629 , G06F3/0685 , G06F9/4403 , G06F9/4418 , G06F11/00 , G06F12/0868 , G06F13/28 , G06F2212/1016 , G06F2212/1028 , G06F2212/1052 , G06F2212/214 , Y02D10/13
摘要： Methods and apparatus for effecting a processor- and platform-assisted NVDIMM solution using standard DRAM and consolidated storage. The methods and apparatus enable selected data in DRAM devices, such as DIMMs to be automatically copied to a persistent storage device such as an SSD in response to detection of a power unavailable event or an operating system error or failure without any operating system intervention. In one aspect, a platform includes a power supply and a temporary power source, such as a capacitor-based energy storage device, a small battery, or a combination of the two, either integrated in the power supply or separate. When power becomes unavailable, the temporary power source is use to continue to provide power to selected components in one or more power protected domains. The energy stored in the temporary power source is sufficient to temporarily power the components to enable DRAM data to be written to the persistent storage device. Upon system restart, the previously-stored DRAM data is restored to one or more DRAM devices from which the data was originally copied.
摘要翻译：使用标准DRAM和统一存储实现处理器和平台辅助NVDIMM解决方案的方法和设备。所述方法和装置使得诸如DIMM之类的DRAM设备中的所选数据能够自动复制到诸如SSD的持久存储设备，以响应于检测到不可用电力事件或操作系统错误或故障，而无需任何操作系统干预。一方面，平台包括集成在电源中或单独的电源和临时电源，诸如基于电容器的能量存储装置，小电池或两者的组合。当电力不可用时，临时电源用于继续向一个或多个电源保护域中的选定组件供电。存储在临时电源中的能量足以临时为组件供电，以使DRAM数据能够写入持久存储设备。在系统重新启动时，先前存储的DRAM数据被恢复到原始复制数据的一个或多个DRAM装置。

83. 发明申请

US20160350002A1 Memory device specific self refresh entry and exit 审中-公开
标题翻译：内存设备特定的自刷新进入和退出
公开(公告)号：US20160350002A1
公开(公告)日：2016-12-01
申请号：US14998058
申请日：2015-12-26
申请人： Intel Corporation
发明人： George Vergis , Kuljit S. Bains , James A. McCall , Murugasamy K. Nachimuthu , Mohan J. Kumar
IPC分类号： G06F3/06
CPC分类号： G06F12/02 , G11C5/04 , G11C11/40615 , G11C11/4074 , G11C2211/4067
摘要： A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.
摘要翻译：系统启用存储设备特定的自刷新进入和退出命令。当共享控制总线（诸如等级上的所有存储设备）中的存储设备进行自刷新时，存储器控制器可以向存储器设备发出具有自刷新退出命令和唯一存储器设备标识符的特定于设备的命令。控制器通过共享控制总线发送命令，只有选定的已识别的存储设备将退出自刷新，而其他设备将忽略该命令并保持自刷新。然后，控制器可以通过共享数据总线与特定存储器设备执行数据访问，而其他存储器件处于自刷新状态。

84. 发明申请

US20160239460A1 METHOD AND APPARATUS FOR SERVER PLATFORM ARCHITECTURES THAT ENABLE SERVICEABLE NONVOLATILE MEMORY MODULES 审中-公开
标题翻译：使用可维修非易失性存储器模块的服务器平台架构的方法和设备
公开(公告)号：US20160239460A1
公开(公告)日：2016-08-18
申请号：US15025988
申请日：2013-11-27
申请人： INTEL CORPORATION
发明人： Dimitrios Ziakas , Bassam N. Coury , Mohan J. Kumar , Murugasamy K. Nachimuthu , Thi Dang , Russell J. Wunderlich
IPC分类号： G06F15/78 , G06F11/16
CPC分类号： G06F15/7803 , G06F11/1068 , G06F11/108 , G06F11/1092 , G06F11/1662 , G06F11/3485 , G06F2201/805
摘要： Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
摘要翻译：实现服务器架构的系统和方法可以方便计算机系统中的存储器组件的维护。这些系统和方法采用非易失性存储/存储模块，其中包括可用于系统内存和大容量存储的非易失性存储器（NVM）以及固件存储器。相应的NVM /存储模块可以被接收在计算机系统的前部或后部装载槽中。该系统和方法进一步采用单插槽，双插槽或四插槽处理器，其中每个处理器通过一个或多个存储器和/或输入端可通信地耦合到布置在前端或后端装载机架中的至少一些NVM /存储模块 /输出（I / O）通道。通过采用可以在计算机系统的前端或后端加载接收的NVM /存储模块，系统和方法提供了存储器组件在实现常规服务器架构的计算机系统中无法实现的可维护性。

85. 发明申请

US20150149735A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20150149735A1
公开(公告)日：2015-05-28
申请号：US13977653
申请日：2013-03-15
申请人： Intel Corporation
发明人： Bill Nale , Murugasamy K. Nachimuthu , Jun Zhu , Tuan M. Quach
IPC分类号： G06F13/16 , G06F12/08
CPC分类号： G06F11/0793 , G06F3/0604 , G06F3/061 , G06F3/0629 , G06F3/0638 , G06F3/0673 , G06F3/0683 , G06F11/0727 , G06F11/0751 , G06F11/0772 , G06F11/079 , G06F12/023 , G06F12/0802 , G06F12/0813 , G06F13/1663 , G06F13/1678 , G06F13/1689 , G06F13/1694 , G06F13/4234 , G06F13/4243 , G06F13/4282 , G06F2212/1044 , G06F2212/2532 , G06F2212/60 , G11C5/04 , G11C5/148 , G11C7/1003 , G11C7/1063 , G11C7/1072 , G11C7/222 , G11C11/40618 , G11C29/023 , G11C29/028 , H04L9/0869
摘要： Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.
摘要翻译：提供了一种用于通过总线耦合到主机存储器控制器的存储器模块中的装置，包括存储器模块控制逻辑，以产生具有大于或等于最小脉冲宽度的脉冲宽度的主机存储器控制器的请求信号，其中所述最小脉冲宽度包括保证所述主机存储器控制器检测到所述请求信号所需的多个时钟周期，并且其中所述请求信号的脉冲宽度除了对所述主机存储器控制器的所述请求信号之外还指示至少一个功能。

87. 发明授权

US12073255B2 Technologies for providing latency-aware consensus management in a disaggregated architecture 有权
公开(公告)号：US12073255B2
公开(公告)日：2024-08-27
申请号：US16460371
申请日：2019-07-02
申请人： Intel Corporation
发明人： Mrittika Ganguli , Murugasamy K. Nachimuthu , Muralidharan Sundararajan , Susanne M. Balle , Mohan J. Kumar
IPC分类号： G06F9/50 , H04L67/1008 , H04L67/1031
CPC分类号： G06F9/505 , H04L67/1008 , H04L67/1031
摘要： Technologies for providing latency-aware consensus management in a disaggregated system include a compute device. The compute device includes circuitry to determine latencies associated with subsystems of the disaggregated system. Additionally, the circuitry is to determine, as a function of the determined latencies, a time period in which a configuration change to the disaggregated system is to reach a consistent state in the subsystems.

88. 发明公开

US20240241761A1 CLOUD-BASED SCALE-UP SYSTEM COMPOSITION 审中-公开
公开(公告)号：US20240241761A1
公开(公告)日：2024-07-18
申请号：US18618901
申请日：2024-03-27
申请人： Intel Corporation
发明人： Mohan J. Kumar , Murugasamy K. Nachimuthu , Krishna Bhuyan
IPC分类号： G06F9/50 , G06F3/06 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/38 , G06F9/4401 , G06F9/455 , G06F9/48 , G06F9/54 , G06F11/07 , G06F11/30 , G06F11/34 , G06F12/02 , G06F12/06 , G06F13/16 , G06F16/174 , G06F21/57 , G06F21/62 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/00 , H01R13/453 , H01R13/631 , H03K19/173 , H03M7/30 , H03M7/40 , H03M7/42 , H04L9/08 , H04L12/28 , H04L12/46 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/14 , G06F11/14 , G06F15/80 , G06F16/28 , H04L9/40 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L47/78 , H04Q11/00
CPC分类号： G06F9/505 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0641 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/45533 , G06F9/4843 , G06F9/4881 , G06F9/5005 , G06F9/5038 , G06F9/5044 , G06F9/5083 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3079 , G06F11/3409 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/453 , H01R13/4536 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/1452 , H05K7/1487 , H05K7/1491 , G06F11/1453 , G06F12/023 , G06F15/80 , G06F16/285 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L47/78 , H04L63/1425 , H04Q11/0005 , H05K7/1447 , H05K7/1492
摘要： Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

89. 发明授权

US11977923B2 Cloud-based scale-up system composition 有权
公开(公告)号：US11977923B2
公开(公告)日：2024-05-07
申请号：US18103739
申请日：2023-01-31
申请人： Intel Corporation
发明人： Mohan J. Kumar , Murugasamy K. Nachimuthu , Krishna Bhuyan
IPC分类号： G06F9/50 , G06F3/06 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/38 , G06F9/4401 , G06F9/455 , G06F9/48 , G06F9/54 , G06F11/07 , G06F11/30 , G06F11/34 , G06F12/02 , G06F12/06 , G06F13/16 , G06F16/174 , G06F21/57 , G06F21/62 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/00 , H01R13/453 , H01R13/631 , H03K19/173 , H03M7/30 , H03M7/40 , H03M7/42 , H04L9/08 , H04L12/28 , H04L12/46 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/14 , G06F11/14 , G06F15/80 , G06F16/28 , H04L9/40 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L47/78 , H04Q11/00
CPC分类号： G06F9/505 , G06F3/0604 , G06F3/0608 , G06F3/0611 , G06F3/0613 , G06F3/0617 , G06F3/0641 , G06F3/0647 , G06F3/065 , G06F3/0653 , G06F3/067 , G06F7/06 , G06F8/65 , G06F8/654 , G06F8/656 , G06F8/658 , G06F9/3851 , G06F9/3891 , G06F9/4401 , G06F9/45533 , G06F9/4843 , G06F9/4881 , G06F9/5005 , G06F9/5038 , G06F9/5044 , G06F9/5083 , G06F9/544 , G06F11/0709 , G06F11/0751 , G06F11/079 , G06F11/3006 , G06F11/3034 , G06F11/3055 , G06F11/3079 , G06F11/3409 , G06F12/0284 , G06F12/0692 , G06F13/1652 , G06F16/1744 , G06F21/57 , G06F21/6218 , G06F21/73 , G06F21/76 , G06T1/20 , G06T1/60 , G06T9/005 , H01R13/453 , H01R13/4536 , H01R13/4538 , H01R13/631 , H03K19/1731 , H03M7/3084 , H03M7/40 , H03M7/42 , H03M7/60 , H03M7/6011 , H03M7/6017 , H03M7/6029 , H04L9/0822 , H04L12/2881 , H04L12/4633 , H04L41/044 , H04L41/0816 , H04L41/0853 , H04L41/12 , H04L43/04 , H04L43/06 , H04L43/08 , H04L43/0894 , H04L47/20 , H04L47/2441 , H04L49/104 , H04L61/5007 , H04L67/10 , H04L67/1014 , H04L67/63 , H04L67/75 , H05K7/1452 , H05K7/1487 , H05K7/1491 , G06F11/1453 , G06F12/023 , G06F15/80 , G06F16/285 , G06F2212/401 , G06F2212/402 , G06F2221/2107 , H04L41/046 , H04L41/0896 , H04L41/142 , H04L47/78 , H04L63/1425 , H04Q11/0005 , H05K7/1447 , H05K7/1492
摘要： Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

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