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81. 发明授权

US08779514B2 Transistor and method for manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08779514B2
公开(公告)日：2014-07-15
申请号：US13144903
申请日：2011-02-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78648 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.
摘要翻译：本发明涉及晶体管及其制造方法。根据本发明的实施例的晶体管可以包括：至少包括晶体管的背栅极，绝缘层和顺序层叠的半导体层的衬底，其中晶体管的背栅极用于调节晶体管的阈值电压晶体管; 形成在所述半导体层上的栅极堆叠，其中所述栅极堆叠包括形成在所述栅极电介质上的栅极电介质和栅电极; 形成在栅叠层的侧壁上的间隔物; 以及分别位于栅极堆叠的两侧的源极区域和漏极区域，其中栅极叠层的高度低于间隔物的高度。该晶体管能够降低栅极叠层的高度，从而提高晶体管的性能。

82. 发明授权

US08686534B2 Trench isolation structure and method for forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US08686534B2
公开(公告)日：2014-04-01
申请号：US13145301
申请日：2011-04-22
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232 , H01L29/02
摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed in the semiconductor substrate and filled with a dielectric layer, where the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
摘要翻译：提供了沟槽隔离结构及其形成方法。沟槽隔离结构包括：半导体衬底和形成在半导体衬底中并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

83. 发明授权

US08652884B2 Semiconductor device structure and method for manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US08652884B2
公开(公告)日：2014-02-18
申请号：US13380975
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/335 , H01L21/70
CPC分类号： H01L27/0207 , H01L21/823437 , H01L21/823475 , H01L27/092 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.
摘要翻译：本发明提出一种半导体器件结构及其制造方法，涉及半导体制造业。该方法包括：提供半导体衬底; 在半导体衬底上形成栅电极线; 在栅电极线的两侧形成侧壁间隔物; 在栅极电极线的两侧在半导体基板上形成源极/漏极区域; 在栅电极线或源极/漏极区上形成接触孔; 并且在形成侧壁间隔物之后但在用于半导体器件结构的FEOL处理完成之前，切断栅电极线以形成电隔离的栅电极。本发明的实施例可用于制造集成电路。

84. 发明授权

US08610248B2 Capacitor structure and method of manufacture 有权
标题翻译：电容器结构及制造方法
公开(公告)号：US08610248B2
公开(公告)日：2013-12-17
申请号：US12993048
申请日：2010-09-21
申请人： Qingqing Liang , Huicai Zhong
发明人： Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/02
CPC分类号： H01L28/90 , H01G4/232 , H01G4/30 , H01G4/33 , H01L28/86
摘要： The presented application discloses a capacitor structure and a method for manufacturing the same. The capacitor structure comprises a plurality of sub-capacitors formed on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween; and a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel, wherein the plurality of sub-capacitors includes a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitor, with the overlapping plate being a second electrode layer, the capacitor structure is characterized in that the first electrode layer and the second electrode layers are made of different conductive materials. The capacitor structure has a small footprint on the chip and a large capacitance value, and can be used as an integrated capacitor in an analogous circuit, an RF circuit, an embedded memory, and the like.
摘要翻译：本申请公开了一种电容器结构及其制造方法。电容器结构包括形成在基板上的多个子电容器，每个子电容器包括顶部电容器板，底部电容器板和夹在其间的电介质层; 以及并联连接多个副电容器的第一电容电极和第二电容电极，其中，所述多个副电容器包括多个第一子电容器和以交替方式堆叠的多个第二子电容器，的第一子电容器具有与下面的第二子电容器的顶部电容器板重叠的底部电容器板，其中重叠板是第一电极层，并且每个第二子电容器具有与电容器结构的特征在于，第一电极层和第二电极层由不同的导电材料制成。电容器结构在芯片上具有小的占地面积和大的电容值，并且可以用作模拟电路，RF电路，嵌入式存储器等中的集成电容器。

85. 发明授权

US08592911B2 Asymmetric semiconductor device having a high-k/metal gate and method of manufacturing the same 有权
标题翻译：具有高k /金属栅极的非对称半导体器件及其制造方法
公开(公告)号：US08592911B2
公开(公告)日：2013-11-26
申请号：US13063717
申请日：2010-09-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/2815 , H01L21/823462 , H01L21/823468 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66659
摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a metal sidewall spacer on the sidewall of a gate electrode on the drain region side. The metal sidewall spacer is made of such metals as Ta, which has an oxygen scavenging effect and can effectively reduce EOT on the drain region side, and thus the ability to control the short channel is effectively increased. In addition, since EOT on the source region side is larger, the carrier mobility of the device will not be degraded. Moreover, such asymmetric device may have a better driving performance.
摘要翻译：提供半导体器件及其制造方法。半导体器件在漏极区侧的栅电极的侧壁上具有金属侧壁间隔物。金属侧壁间隔物由具有除氧效果的Ta等金属制成，能够有效地减少漏区侧面的EOT，有效地提高控制短路的能力。此外，由于源区域侧的EOT较大，所以器件的载流子迁移率不会降低。此外，这种不对称装置可能具有更好的驱动性能。

86. 发明授权

US08557677B2 Stack-type semiconductor device and method for manufacturing the same 有权
标题翻译：叠层型半导体器件及其制造方法
公开(公告)号：US08557677B2
公开(公告)日：2013-10-15
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

87. 发明授权

US08513780B2 Semiconductor device having inter-level dielectric layer with hole-sealing and method for manufacturing the same 有权
标题翻译：具有空穴密封的层间电介质层的半导体装置及其制造方法
公开(公告)号：US08513780B2
公开(公告)日：2013-08-20
申请号：US13141001
申请日：2011-02-26
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L23/58 , H01L27/088 , H01L21/70 , H01L29/40 , H01L21/4763
CPC分类号： H01L21/7682 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses an inter-level dielectric layer for a semiconductor device, a method for manufacturing the same and a semiconductor device having said inter-level dielectric layer. The method lies in forming non-interconnected holes within a dielectric layer, and these holes may be filled with porous low-k dielectric material with a much lower dielectric constant, or forming holes within the dielectric layer by filling the upper parts of the holes. The inter-level dielectric layer in such a structure has a much lower dielectric constant, reduces RC delay between devices of integrated circuits and also is easy to integrate; besides, since the holes within the dielectric layer are non-interconnected, they shall not cause change to the dielectric constant of the dielectric material or a short circuit between wires, thus the device shall have better stability and reliability which then improve performance of the circuit.
摘要翻译：本发明公开了一种用于半导体器件的层间电介质层，其制造方法和具有所述层间电介质层的半导体器件。该方法在于在电介质层内形成非互连的孔，并且这些孔可以填充具有低得多的介电常数的多孔低k电介质材料，或者通过填充孔的上部而在电介质层内形成孔。这种结构中的层间电介质层具有低得多的介电常数，降低了集成电路器件之间的RC延迟，并且易于集成; 此外，由于电介质层内的孔不互连，它们不会导致电介质材料的介电常数或电线之间的短路，因此该装置应具有更好的稳定性和可靠性，从而提高电路的性能。

88. 发明授权

US08513742B2 Method for manufacturing contact and semiconductor device having said contact 有权
标题翻译：具有所述接触的接触和半导体器件的制造方法
公开(公告)号：US08513742B2
公开(公告)日：2013-08-20
申请号：US13144887
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L27/088
CPC分类号： H01L21/76816 , H01L21/76877 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a method for manufacturing a contact and a semiconductor device having said contact. The present invention proposes to form first a trench contract of relatively large size, then to form one or more dielectric layer(s) within the trench contact, and then to remove the upper part of the dielectric layer(s) and to fill the same with a conductive material. The use of such a method makes it easy to form a trench contact of relatively large size which is easy for manufacturing; besides, since dielectric layer(s) is/are formed in the trench contact, thence capacitance between a source/drain trench contact and a gate electrode is reduced accordingly.
摘要翻译：本发明涉及一种用于制造接触的方法和具有所述接触的半导体器件。本发明提出首先形成相对大尺寸的沟槽接合，然后在沟槽接触中形成一个或多个电介质层，然后去除电介质层的上部并填充相同的电介质层与导电材料。使用这种方法可以容易地形成容易制造的较大尺寸的沟槽接触; 此外，由于在沟槽接触中形成介电层，所以源极/漏极沟槽接触和栅电极之间的电容相应地减小。

89. 发明申请

US20130140624A1 Semiconductor Structure and Method for Forming The Semiconductor Structure 有权
标题翻译：用于形成半导体结构的半导体结构和方法
公开(公告)号：US20130140624A1
公开(公告)日：2013-06-06
申请号：US13807010
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/28008 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/458 , H01L29/4908 , H01L29/66666 , H01L29/78642
摘要： The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.
摘要翻译：本发明公开了一种半导体结构，包括：衬底，导体层和围绕衬底上的导体层的电介质层; 覆盖所述导体层和所述电介质层的第一绝缘层; 形成在第一绝缘层上的栅极导体层和围绕栅极导体层的电介质层; 以及覆盖所述栅极导体层和围绕所述栅极导体层的所述电介质层的第二绝缘层; 其中填充有半导体材料的通孔垂直地穿过栅极导体层，通孔的底部停在导体层上，并且用作漏极/源极的第一导体插塞设置在通孔的顶部 ; 和用作源/漏电极的第二导体插头与导体层电接触，并且用作栅电极的第三导体插头电接触栅极导体层。

90. 发明授权

US08455323B2 Method for manufacturing semiconductor wafer 有权
标题翻译：制造半导体晶片的方法
公开(公告)号：US08455323B2
公开(公告)日：2013-06-04
申请号：US13201125
申请日：2011-02-25
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L21/336
CPC分类号： H01L21/3221
摘要： There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.
摘要翻译：提供了一种制造半导体晶片的方法，包括：进行加热，使得金属溶解到晶片的半导体中以形成半导体 - 金属化合物; 并进行冷却，使得所形成的半导体 - 金属化合物逆向熔融以形成金属和半导体的混合物。根据本发明的实施例，可以实现适用于半导体制造的高纯度晶片。

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