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81. 发明申请

US20090267135A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090267135A1
公开(公告)日：2009-10-29
申请号：US12408249
申请日：2009-03-20
申请人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Hideaki Aochi , Megumi Ishiduki , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Hideaki Aochi , Megumi Ishiduki , Yasuyuki Matsuoka
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/11578 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L27/11582
摘要： A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction. The second layer includes: a plurality of second conductive layers extending in parallel to the substrate and laminated in a direction perpendicular to the substrate, the second conductive layers being formed in the same layer as the plurality of first conductive layers; and a second insulation layer formed on an upper layer of the plurality of second conductive layers. Respective ends of the second conductive layers are formed to align along a straight line extending in a direction substantially perpendicular to the substrate at a predetermined area.
摘要翻译：非易失性半导体存储装置包括第一层和第二层。第一层包括：多个第一导电层，其平行于衬底延伸并且在垂直于衬底的方向上层压; 形成在所述多个第一导电层的上层上的第一绝缘层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷累积层。第一导电层的相应端部在第一方向上相对于彼此以逐步的方式形成。第二层包括：多个第二导电层，其平行于衬底延伸并且在垂直于衬底的方向上层叠，第二导电层形成在与多个第一导电层相同的层中; 以及形成在所述多个第二导电层的上层上的第二绝缘层。形成第二导电层的相应端，沿着在预定区域上基本上垂直于衬底的方向延伸的直线对齐。

82. 发明申请

US20090230462A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：US20090230462A1
公开(公告)日：2009-09-17
申请号：US12393509
申请日：2009-02-26
申请人： Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Hiroyasu Tanaka , Masaru Kidoh , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/11578 , H01L27/11582
摘要： Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.
摘要翻译：每个存储器串包括：在垂直方向上延伸到衬底的第一柱状半导体层; 多个第一导电层，其形成为夹着具有电荷陷阱层的绝缘层并以二维方式扩展; 第二柱状半导体层，其与所述第一柱状半导体层的顶表面接触并且在垂直方向上延伸到所述衬底; 以及多个第二导电层，其形成为与第二柱状半导体层夹着绝缘层，并且形成为沿与垂直方向正交的第一方向延伸的条纹图案。多个第一导电层的第一方向的端部相对于彼此分步地形成，多个第二导电层的整体形成在第一导电层的顶层的正上方的区域中，并且多个第一导电层和多个第二导电层被与多个第一导电层和第二导电层连续形成的保护绝缘层覆盖。

83. 发明申请

US20090224309A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20090224309A1
公开(公告)日：2009-09-10
申请号：US12389977
申请日：2009-02-20
申请人： Masaru Kidoh , Masaru Kito , Ryota Katsumata , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Masaru Kidoh , Masaru Kito , Ryota Katsumata , Yoshiaki Fukuzumi , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L29/792 , H01L21/20 , H01L21/336
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so that the semiconductor layer infills the first hole and the second hole after the removal of the sacrificing layer
摘要翻译：一种制造非易失性半导体存储装置的方法，包括：形成第一导电层，使其通过第一绝缘层沿上下方向夹持; 形成第一孔，使其穿透第一绝缘层和第一导电层; 在面向所述第一孔的侧壁上形成第一侧壁绝缘层; 形成牺牲层，使牺牲层填充第一孔; 在牺牲层的上层上形成第二导电层，使得第二导电层在上下方向上被第二绝缘层夹持; 在与所述第一孔匹配的位置上形成第二孔，使得所述第二孔穿过所述第二绝缘层和所述第二导电层; 在面向所述第二孔的侧壁上形成第二侧壁绝缘层; 在形成第二侧壁绝缘层之后去除牺牲层; 以及形成半导体层，使得半导体层在去除牺牲层之后填充第一孔和第二孔

84. 发明申请

US20090101969A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090101969A1
公开(公告)日：2009-04-23
申请号：US12248577
申请日：2008-10-09
申请人： Ryota KATSUMATA , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
发明人： Ryota KATSUMATA , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Hideaki Aochi , Yasuyuki Matsuoka
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0657 , H01L29/0692 , H01L29/4238 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a semiconductor substrate; a first conductive layer provided on a surface of the substrate and serving as one of a source and a drain; a first insulating film provided on the first conductive layer; a gate electrode film provided on the first insulating film; a second insulating film provided on the gate electrode film; a gate opening provided so as to penetrate the second insulating film, the gate electrode film and the first insulating film to expose a part of the first conductive layer; a recess provided in the surface of the first conductive layer just below the gate opening; a gate insulator provided on the side surface of the gate opening and having a projecting shape at a portion between the first insulating film and the recess; a second conductive layer buried in the recess and in a bottom of the gate opening so as to be in contact with the gate insulator, and serving as the one of the source and the drain while being in contact with the first conductive layer; a channel which is buried in the gate opening above the second conductive layer so as to face the gate electrode film with the gate insulator therebetween, and which has a channel layer generated therein, the channel layer allowing majority carriers to flow between the source and the drain in response to a voltage applied to the gate; and a third conductive layer buried in the gate opening above the channel so as to be in contact with the gate insulator to serve as the other one of the source and the drain.
摘要翻译：一种半导体器件，包括：半导体衬底; 设置在所述基板的表面上并用作源极和漏极之一的第一导电层; 设置在所述第一导电层上的第一绝缘膜; 设置在所述第一绝缘膜上的栅电极膜; 设置在栅电极膜上的第二绝缘膜; 设置为穿透第二绝缘膜的栅极开口，栅极电极膜和第一绝缘膜，以暴露第一导电层的一部分; 设置在所述第一导电层的位于所述栅极开口正下方的表面中的凹部; 栅极绝缘体，其设置在所述栅极开口的侧表面上，并且在所述第一绝缘膜和所述凹部之间的部分处具有突出形状; 第二导电层，其被埋置在所述凹部中并且位于所述栅极开口的底部以与所述栅极绝缘体接触，并且在与所述第一导电层接触的同时用作所述源极和漏极中的一个; 埋入在第二导电层上方的栅极开口中以与门极绝缘体相对的栅极电极膜并且其中产生沟道层的沟道，该沟道层允许多数载流子在源极和源极之间流动响应于施加到门的电压而漏极; 以及掩埋在沟道上方的栅极开口中的第三导电层，以便与栅极绝缘体接触以用作源极和漏极中的另一个。

85. 发明申请

US20080315291A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080315291A1
公开(公告)日：2008-12-25
申请号：US12140734
申请日：2008-06-17
申请人： Masaru KITO , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
发明人： Masaru KITO , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
IPC分类号： H01L29/00 , H01L21/31
CPC分类号： H01L27/105 , H01L21/02161 , H01L21/02164 , H01L21/0217 , H01L21/31645 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device has a plurality of memory strings each including a plurality of electrically rewritable memory cells serially connected. The memory string includes a columnar semiconductor portion extending in the vertical direction from a substrate, a first charge storage layer formed adjacent to the columnar semiconductor portion and configured to accumulate charge, a first block insulator formed adjacent to the first charge storage layer, and a first conductor formed adjacent to the first block insulator.
摘要翻译：非易失性半导体存储器件具有多个存储串，每个存储串包括串联连接的多个电可重写存储器单元。存储器串包括从基板沿垂直方向延伸的柱状半导体部分，与柱状半导体部分相邻形成并构成为积蓄电荷的第一电荷存储层，与第一电荷存储层相邻形成的第一块绝缘体，第一导体与第一块绝缘体相邻形成。

86. 发明申请

US20080180994A1 MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING SAME 有权
标题翻译：存储器系统，半导体存储器件及其驱动方法
公开(公告)号：US20080180994A1
公开(公告)日：2008-07-31
申请号：US11955900
申请日：2007-12-13
申请人： Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Hideaki Aochi , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
发明人： Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Masaru Kito , Hideaki Aochi , Yoshiaki Fukuzumi , Yasuyuki Matsuoka
IPC分类号： G11C11/34 , H01L29/76 , G11C8/00
CPC分类号： H01L27/115 , G11C7/18 , G11C8/08 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device has a semiconductor substrate, first select transistors formed on the surface of said semiconductor substrate, first dummy transistors formed above said first select transistors, a plurality of memory cell transistors formed above said first dummy transistors so as to extend in a direction perpendicular to the surface of said semiconductor substrate, each of said memory cell transistor including an insulating layer having a charge-accumulating function, second dummy transistors formed above said memory cell transistors, and second select transistors formed above said second dummy transistors; wherein a first potential is provided to the gate electrodes of said first select transistors and the gate electrodes of said first dummy transistors and a second potential is provided to the gate electrodes of said second select transistors and the gate electrodes of said second dummy transistors at the time of write operation to write data to said memory cell transistors.
摘要翻译：半导体存储器件具有半导体衬底，形成在所述半导体衬底的表面上的第一选择晶体管，形成在所述第一选择晶体管上方的第一虚拟晶体管，形成在所述第一虚拟晶体管上方的多个存储单元晶体管，垂直于所述半导体衬底的表面，每个所述存储单元晶体管包括具有电荷累积功能的绝缘层，形成在所述存储单元晶体管上方的第二虚拟晶体管以及形成在所述第二虚设晶体管上方的第二选择晶体管; 其中第一电位被提供给所述第一选择晶体管的栅电极和所述第一虚拟晶体管的栅电极，并且第二电位被提供给所述第二选择晶体管的栅极和所述第二虚设晶体管的栅电极写入操作的时间将数据写入到所述存储单元晶体管。

87. 发明授权

US08791464B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08791464B2
公开(公告)日：2014-07-29
申请号：US12820371
申请日：2010-06-22
申请人： Tomoko Fujiwara , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoko Fujiwara , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a stacked structure, a semiconductor pillar, a memory layer and an outer insulating film. The stacked structure includes a plurality of electrode films and a plurality of interelectrode insulating films alternately stacked in a first direction. The semiconductor pillar pierces the stacked structure in the first direction. The memory layer is provided between the electrode films and the semiconductor pillar. The outer insulating film is provided between the electrode films and the memory layer. The device includes a first region and a second region. An outer diameter of the outer insulating film along a second direction perpendicular to the first direction in the first region is larger than that in the second region. A thickness of the outer insulating film along the second direction in the first region is thicker than that in the second region.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括堆叠结构，半导体柱，存储层和外部绝缘膜。堆叠结构包括沿第一方向交替堆叠的多个电极膜和多个电极间绝缘膜。半导体柱沿第一方向刺穿层叠结构。存储层设置在电极膜和半导体柱之间。外绝缘膜设置在电极膜和存储层之间。该装置包括第一区域和第二区域。沿着与第一区域的第一方向垂直的第二方向的外绝缘膜的外径大于第二区域的外径。第一区域中沿着第二方向的外绝缘膜的厚度比第二区域厚。

88. 发明授权

US08653582B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08653582B2
公开(公告)日：2014-02-18
申请号：US12724713
申请日：2010-03-16
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于第一方向第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。

89. 发明授权

US08605508B2 Non-volatile semiconductor storage device having control circuit to control voltages to select transistor for erase operation 有权
标题翻译：具有控制电路以控制电压以选择用于擦除操作的晶体管的非易失性半导体存储装置
公开(公告)号：US08605508B2
公开(公告)日：2013-12-10
申请号：US13463889
申请日：2012-05-04
申请人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
发明人： Kiyotaro Itagaki , Yoshihisa Iwata , Hiroyasu Tanaka , Masaru Kidoh , Masaru Kito , Ryota Katsumata , Hideaki Aochi , Akihiro Nitayama , Takashi Maeda , Tomoo Hishida
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30
摘要： A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
摘要翻译：非易失性半导体存储装置包括：包括串联连接的多个存储单元的存储串; 第一选择晶体管，其一端连接到存储器串的一端; 第一布线，其一端连接到第一选择晶体管的另一端; 连接到第一选择晶体管的栅极的第二布线。控制电路被配置为在保持第一布线的电压大于第二布线的电压一定电位差的同时，在擦除操作中提高第二布线和第一布线的电压。一定的电位差是导致GIDL电流的电位差。

90. 发明授权

US08569133B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08569133B2
公开(公告)日：2013-10-29
申请号：US13366509
申请日：2012-02-06
申请人： Masaru Kito , Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Hideaki Aochi
发明人： Masaru Kito , Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Yosuke Komori , Hideaki Aochi
IPC分类号： H01L21/336
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.
摘要翻译：非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。每个存储器串都具有第一半导体层，该第一半导体层具有相对于基板在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

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