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81. 发明申请

US20100208528A1 SEMICONDUCTOR DEVICE HAVING NONVOLATILE MEMORY ELEMENT AND DATA PROCESSING SYSTEM INCLUDING THE SAME 有权
公开(公告)号：US20100208528A1
公开(公告)日：2010-08-19
申请号：US12695784
申请日：2010-01-28
申请人： Yoshio Mizukane , Hiroki Fujisawa
发明人： Yoshio Mizukane , Hiroki Fujisawa
IPC分类号： G11C7/10 , G11C17/16 , G11C7/00
CPC分类号： G11C11/4072 , G11C7/1045 , G11C7/1066 , G11C7/20
摘要： A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.

82. 发明申请

US20100045359A1 CALIBRATION CIRCUIT 失效
标题翻译：校准电路
公开(公告)号：US20100045359A1
公开(公告)日：2010-02-25
申请号：US12611598
申请日：2009-11-03
申请人： Hideyuki Yoko , Hiroki Fujisawa
发明人： Hideyuki Yoko , Hiroki Fujisawa
IPC分类号： G06G7/12
CPC分类号： H03F1/56 , H03F2200/366 , H03F2200/453 , H03F2200/456
摘要： To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.
摘要翻译：包括具有与构成输出缓冲器的上拉电路基本相同的电路配置的第一复制缓冲器和具有与构成输出缓冲器的下拉电路基本相同的电路配置的第二复制缓冲器。当发出第一校准命令ZQCS时，控制信号ACT1或ACT2被激活，并且对于第一副本缓冲器或第二副本缓冲器执行校准操作。当发出第二校准命令ZQCL时，控制信号ACT1，ACT2都被激活，并且对于第一副本缓冲器和第二副本缓冲器都执行校准操作。

83. 发明授权

US07639560B2 Output control signal generating circuit 有权
标题翻译：输出控制信号发生电路
公开(公告)号：US07639560B2
公开(公告)日：2009-12-29
申请号：US12198380
申请日：2008-08-26
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used to take in a read command. The timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits. With this arrangement, a latch margin of a first latch circuit does not depend on the cycle of an external clock. Accordingly, even when a clock has a very high speed, the output can be controlled correctly.
摘要翻译：输出控制信号发生电路包括级联连接的锁存电路和定时信号产生电路，其基于从第一相位相位提前相位的第二时钟产生要提供给锁存电路的定时信号时钟用于读取命令。定时信号发生电路将要提供给包括在锁存电路中的相对前级锁存电路的定时信号的相位延迟到要提供给包括在锁存器中的相对较后级锁存器电路的定时信号的相位电路。利用这种布置，第一锁存电路的锁存边缘不依赖于外部时钟的周期。因此，即使当时钟具有非常高的速度时，可以正确地控制输出。

84. 发明授权

US07630275B2 Latency counter 失效
标题翻译：延迟计数器
公开(公告)号：US07630275B2
公开(公告)日：2009-12-08
申请号：US11882801
申请日：2007-08-06
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： G11C8/00
CPC分类号： G11C8/18 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： A latency counter includes: a point-shift type FIFO circuit having plural latch circuits connected in parallel, each latch circuit including an input gate and an output gate, and having an internal command MDRDT supplied in common to the input gates; and a selector that makes any one of the input gates and any one of the output gates conductive. The selector includes a counter that changes over between a selection operation of selecting the input gate and a selection operation of selecting the output gate, and the counter outputs a count value in a binary format synchronously with an internal clock ICLK. Because the binary-format counter is used in this way, the count value itself does not cause an error.
摘要翻译：延迟计数器包括：具有并联连接的多个锁存电路的点移型FIFO电路，每个锁存电路包括输入门和输出门，并且具有向输入门共同提供的内部命令MDRDT; 以及选择器，其使输入栅极和输出栅极中的任一个导通。选择器包括在选择输入门的选择操作和选择输出门的选择操作之间切换的计数器，并且计数器以与内部时钟ICLK同步的二进制格式输出计数值。因为二进制格式计数器以这种方式使用，所以计数值本身不会引起错误。

85. 发明申请

US20090289499A1 Prevention of the propagation of power supply noise from one output circuit to another in a semiconductor device 有权
标题翻译：在半导体器件中防止电源噪声从一个输出电路传播到另一个输出电路
公开(公告)号：US20090289499A1
公开(公告)日：2009-11-26
申请号：US12453772
申请日：2009-05-21
申请人： Takenori Sato , Hiroki Fujisawa
发明人： Takenori Sato , Hiroki Fujisawa
IPC分类号： H02J1/00
CPC分类号： H02J1/00 , Y10T307/305
摘要： A semiconductor device is disclosed. A first power supply wiring for connecting between a first output circuit consisting of a predetermined number of output circuits and a first power supply pad which corresponds to the first output circuit, is connected via a resistor with a second power supply wiring for connecting between a second output circuit consisting of a predetermined number of output circuit and a second power supply pad which corresponds to the second output circuit. Thus, power supply noise that is to be propagated to certain output circuits via in-chip output power supply wirings can be reduced.
摘要翻译：公开了一种半导体器件。用于连接由预定数量的输出电路组成的第一输出电路和对应于第一输出电路的第一电源焊盘之间的第一电源布线经由电阻器与第二电源布线连接，用于连接第二电源布线输出电路由预定数量的输出电路和对应于第二输出电路的第二电源焊盘构成。因此，可以减少通过片上输出电源布线传播到某些输出电路的电源噪声。

86. 发明授权

US07612579B2 Output circuit of semiconductor device and semiconductor device including thereof 有权
标题翻译：半导体装置的输出电路及其半导体装置
公开(公告)号：US07612579B2
公开(公告)日：2009-11-03
申请号：US11889837
申请日：2007-08-16
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C11/4093 , H04L25/0278 , H04L25/028
摘要： An output circuit includes a counter circuit that generates an ODT control signal ODTa, plural driver circuits having the ODT function, a synchronizing circuit that synchronizes a signal transmitted from the counter circuit to the driver circuit with an internal clock DLL, a first selecting circuit that activates one of plural ODT selection signals ODTb and ODTc based on the ODT control signal ODTa, and a second selecting circuit that selects a driver circuit to be used out of the plural driver circuits based on the activated ODT selection signal. The first selecting circuit is provided between the counter circuit and the synchronizing circuit, and the second selecting circuit is provided between the synchronizing circuit and the driver circuit.
摘要翻译：输出电路包括产生ODT控制信号ODTa的计数器电路，具有ODT功能的多个驱动电路，使从计数器电路发送到驱动器电路的信号与内部时钟DLL同步的同步电路，第一选择电路，基于ODT控制信号ODTa激活多个ODT选择信号ODTb和ODTc中的一个，以及第二选择电路，其基于激活的ODT选择信号选择要从多个驱动器电路中使用的驱动器电路。第一选择电路设置在计数器电路和同步电路之间，第二选择电路设置在同步电路和驱动器电路之间。

87. 发明授权

US07495453B2 Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit 有权
标题翻译：用于半导体器件的输出电路，具有输出电路的半导体器件以及调整输出电路特性的方法
公开(公告)号：US07495453B2
公开(公告)日：2009-02-24
申请号：US11783787
申请日：2007-04-12
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： G01R35/00 , G01R31/26
CPC分类号： H03H11/28 , G01R31/31713 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , H03K19/0005
摘要： To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.
摘要翻译：减少校准输出电路所需的电路规模，并减少校准操作所需的时间。本发明包括连接到数据引脚的第一输出缓冲器和第二输出缓冲器以及连接到校准引脚的校准电路。第一输出缓冲器和第二输出缓冲器包括多个单元缓冲器。单元缓冲器具有相互相同的电路结构。利用这种布置，基于使用校准电路的校准操作，可以将第一输出缓冲器和第二输出缓冲器的阻抗设置为共同的。因此，可以减少校准操作所需的电路规模和校准操作所需的时间。

88. 发明申请

US20090016146A1 Latency counter, semiconductor memory device including the same, and data processing system 有权
标题翻译：延迟计数器，包括其的半导体存储器件和数据处理系统
公开(公告)号：US20090016146A1
公开(公告)日：2009-01-15
申请号：US12216675
申请日：2008-07-09
申请人： Hiroki Fujisawa
发明人： Hiroki Fujisawa
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A latency counter includes: a frequency-dividing circuit that generates a plurality of divided clocks LCLKE and LCLKO of which the phases differ each other based on an internal clock LCLK; and frequency-divided counter circuits each of which counts a latency of an internal command based on the corresponding divided clocks LCLKE and LCLKO. Thus, the counting of the latency is performed based not on the internal clock LCLK itself but on the divided clocks LCLKE and LCLKO obtained by frequency-dividing the internal clock LCLK. Thus, even when a frequency of the internal clock LCLK is high, an operation margin can be sufficiently secured.
摘要翻译：延迟计数器包括：分频电路，其基于内部时钟LCLK产生相位彼此相对的多个分频时钟LCLKE和LCLKO; 以及分频计数器电路，每个计数器电路根据对应的分频时钟LCLKE和LCLKO计数内部命令的等待时间。因此，等待时间的计数不是基于内部时钟LCLK本身而是通过对内部时钟LCLK进行分频而获得的分频时钟LCLKE和LCLKO进行的。因此，即使当内部时钟LCLK的频率高时，也可以充分确保操作余量。

89. 发明申请

US20090009213A1 Calibration circuit, semiconductor device including the same, and data processing system 有权
标题翻译：校准电路，包括相同的半导体器件和数据处理系统
公开(公告)号：US20090009213A1
公开(公告)日：2009-01-08
申请号：US12213962
申请日：2008-06-26
申请人： Fumiyuki Osanai , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Hiroki Fujisawa
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter that forcibly activates the latch circuits in response to a lapse of a predetermined period since issuance of the calibration command. Thereby, even when the adjustment is not completed during one calibration period, a subsequent calibration operation can be executed from a previous point.
摘要翻译：校准电路包括：副本缓冲器; 一个改变复制缓冲器阻抗代码的升降计数器; 每个保持阻抗代码的锁存电路; 终端确定电路，响应于所述副本缓冲器的阻抗调整的完成来激活所述锁存电路; 以及32个tCK循环计数器，其响应于自发出校准命令而经过预定时间段而强制地启动锁存电路。因此，即使在一个校准周期期间调整未完成，也可以从先前的点执行随后的校准操作。

90. 发明授权

US07450446B2 Semiconductor memory device having delay circuit 有权
标题翻译：具有延迟电路的半导体存储器件
公开(公告)号：US07450446B2
公开(公告)日：2008-11-11
申请号：US11598566
申请日：2006-11-14
申请人： Hiromasa Noda , Hiroki Fujisawa
发明人： Hiromasa Noda , Hiroki Fujisawa
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C29/026 , G11C29/028 , G11C29/50012
摘要： Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock signal. The reference signal indicates a reference delay time representing the clock period. The delay circuit configured to delay input signal for a delay time to generate a delayed signal in accordance with the reference signal. The delay time is obtainable by multiplying the reference delay time by a positive integer.
摘要翻译：公开了一种被配置为根据具有时钟周期的时钟信号来延迟输入信号的半导体存储器件。半导体存储器件包括参考信号发生器和延迟电路。参考信号发生器被配置为根据时钟信号产生参考信号。参考信号表示表示时钟周期的参考延迟时间。延迟电路被配置为延迟输入信号一段延迟时间，以根据该参考信号产生延迟的信号。延迟时间可以通过将参考延迟时间乘以正整数来获得。

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